/**
  ******************************************************************************
  * @file    psram_reg.h
  * @version V1.0
  * @date    2021-11-09
  * @brief   This file is the description of.IP register
  ******************************************************************************
  * @attention
  *
  * <h2><center>&copy; COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
  *   1. Redistributions of source code must retain the above copyright notice,
  *      this list of conditions and the following disclaimer.
  *   2. Redistributions in binary form must reproduce the above copyright notice,
  *      this list of conditions and the following disclaimer in the documentation
  *      and/or other materials provided with the distribution.
  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
  *      may be used to endorse or promote products derived from this software
  *      without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  ******************************************************************************
  */
#ifndef __PSRAM_REG_H__
#define __PSRAM_REG_H__

#include "bl616.h"

/* 0x0 : psram_configure */
#define PSRAM_CONFIGURE_OFFSET        (0x0)
#define PSRAM_REG_VENDOR_SEL          PSRAM_REG_VENDOR_SEL
#define PSRAM_REG_VENDOR_SEL_POS      (0U)
#define PSRAM_REG_VENDOR_SEL_LEN      (3U)
#define PSRAM_REG_VENDOR_SEL_MSK      (((1U << PSRAM_REG_VENDOR_SEL_LEN) - 1) << PSRAM_REG_VENDOR_SEL_POS)
#define PSRAM_REG_VENDOR_SEL_UMSK     (~(((1U << PSRAM_REG_VENDOR_SEL_LEN) - 1) << PSRAM_REG_VENDOR_SEL_POS))
#define PSRAM_REG_AP_MR               PSRAM_REG_AP_MR
#define PSRAM_REG_AP_MR_POS           (4U)
#define PSRAM_REG_AP_MR_LEN           (3U)
#define PSRAM_REG_AP_MR_MSK           (((1U << PSRAM_REG_AP_MR_LEN) - 1) << PSRAM_REG_AP_MR_POS)
#define PSRAM_REG_AP_MR_UMSK          (~(((1U << PSRAM_REG_AP_MR_LEN) - 1) << PSRAM_REG_AP_MR_POS))
#define PSRAM_REG_WB_REG_SEL          PSRAM_REG_WB_REG_SEL
#define PSRAM_REG_WB_REG_SEL_POS      (8U)
#define PSRAM_REG_WB_REG_SEL_LEN      (3U)
#define PSRAM_REG_WB_REG_SEL_MSK      (((1U << PSRAM_REG_WB_REG_SEL_LEN) - 1) << PSRAM_REG_WB_REG_SEL_POS)
#define PSRAM_REG_WB_REG_SEL_UMSK     (~(((1U << PSRAM_REG_WB_REG_SEL_LEN) - 1) << PSRAM_REG_WB_REG_SEL_POS))
#define PSRAM_REG_CONFIG_W_PUSLE      PSRAM_REG_CONFIG_W_PUSLE
#define PSRAM_REG_CONFIG_W_PUSLE_POS  (12U)
#define PSRAM_REG_CONFIG_W_PUSLE_LEN  (1U)
#define PSRAM_REG_CONFIG_W_PUSLE_MSK  (((1U << PSRAM_REG_CONFIG_W_PUSLE_LEN) - 1) << PSRAM_REG_CONFIG_W_PUSLE_POS)
#define PSRAM_REG_CONFIG_W_PUSLE_UMSK (~(((1U << PSRAM_REG_CONFIG_W_PUSLE_LEN) - 1) << PSRAM_REG_CONFIG_W_PUSLE_POS))
#define PSRAM_REG_CONFIG_R_PUSLE      PSRAM_REG_CONFIG_R_PUSLE
#define PSRAM_REG_CONFIG_R_PUSLE_POS  (13U)
#define PSRAM_REG_CONFIG_R_PUSLE_LEN  (1U)
#define PSRAM_REG_CONFIG_R_PUSLE_MSK  (((1U << PSRAM_REG_CONFIG_R_PUSLE_LEN) - 1) << PSRAM_REG_CONFIG_R_PUSLE_POS)
#define PSRAM_REG_CONFIG_R_PUSLE_UMSK (~(((1U << PSRAM_REG_CONFIG_R_PUSLE_LEN) - 1) << PSRAM_REG_CONFIG_R_PUSLE_POS))
#define PSRAM_STS_CONFIG_W_DONE       PSRAM_STS_CONFIG_W_DONE
#define PSRAM_STS_CONFIG_W_DONE_POS   (14U)
#define PSRAM_STS_CONFIG_W_DONE_LEN   (1U)
#define PSRAM_STS_CONFIG_W_DONE_MSK   (((1U << PSRAM_STS_CONFIG_W_DONE_LEN) - 1) << PSRAM_STS_CONFIG_W_DONE_POS)
#define PSRAM_STS_CONFIG_W_DONE_UMSK  (~(((1U << PSRAM_STS_CONFIG_W_DONE_LEN) - 1) << PSRAM_STS_CONFIG_W_DONE_POS))
#define PSRAM_STS_CONFIG_R_DONE       PSRAM_STS_CONFIG_R_DONE
#define PSRAM_STS_CONFIG_R_DONE_POS   (15U)
#define PSRAM_STS_CONFIG_R_DONE_LEN   (1U)
#define PSRAM_STS_CONFIG_R_DONE_MSK   (((1U << PSRAM_STS_CONFIG_R_DONE_LEN) - 1) << PSRAM_STS_CONFIG_R_DONE_POS)
#define PSRAM_STS_CONFIG_R_DONE_UMSK  (~(((1U << PSRAM_STS_CONFIG_R_DONE_LEN) - 1) << PSRAM_STS_CONFIG_R_DONE_POS))
#define PSRAM_REG_CONFIG_REQ          PSRAM_REG_CONFIG_REQ
#define PSRAM_REG_CONFIG_REQ_POS      (16U)
#define PSRAM_REG_CONFIG_REQ_LEN      (1U)
#define PSRAM_REG_CONFIG_REQ_MSK      (((1U << PSRAM_REG_CONFIG_REQ_LEN) - 1) << PSRAM_REG_CONFIG_REQ_POS)
#define PSRAM_REG_CONFIG_REQ_UMSK     (~(((1U << PSRAM_REG_CONFIG_REQ_LEN) - 1) << PSRAM_REG_CONFIG_REQ_POS))
#define PSRAM_REG_CONFIG_GNT          PSRAM_REG_CONFIG_GNT
#define PSRAM_REG_CONFIG_GNT_POS      (17U)
#define PSRAM_REG_CONFIG_GNT_LEN      (1U)
#define PSRAM_REG_CONFIG_GNT_MSK      (((1U << PSRAM_REG_CONFIG_GNT_LEN) - 1) << PSRAM_REG_CONFIG_GNT_POS)
#define PSRAM_REG_CONFIG_GNT_UMSK     (~(((1U << PSRAM_REG_CONFIG_GNT_LEN) - 1) << PSRAM_REG_CONFIG_GNT_POS))
#define PSRAM_REG_X16_MODE            PSRAM_REG_X16_MODE
#define PSRAM_REG_X16_MODE_POS        (18U)
#define PSRAM_REG_X16_MODE_LEN        (1U)
#define PSRAM_REG_X16_MODE_MSK        (((1U << PSRAM_REG_X16_MODE_LEN) - 1) << PSRAM_REG_X16_MODE_POS)
#define PSRAM_REG_X16_MODE_UMSK       (~(((1U << PSRAM_REG_X16_MODE_LEN) - 1) << PSRAM_REG_X16_MODE_POS))
#define PSRAM_REG_WB_HYPER3           PSRAM_REG_WB_HYPER3
#define PSRAM_REG_WB_HYPER3_POS       (19U)
#define PSRAM_REG_WB_HYPER3_LEN       (1U)
#define PSRAM_REG_WB_HYPER3_MSK       (((1U << PSRAM_REG_WB_HYPER3_LEN) - 1) << PSRAM_REG_WB_HYPER3_POS)
#define PSRAM_REG_WB_HYPER3_UMSK      (~(((1U << PSRAM_REG_WB_HYPER3_LEN) - 1) << PSRAM_REG_WB_HYPER3_POS))
#define PSRAM_REG_PCK_S_DIV           PSRAM_REG_PCK_S_DIV
#define PSRAM_REG_PCK_S_DIV_POS       (20U)
#define PSRAM_REG_PCK_S_DIV_LEN       (3U)
#define PSRAM_REG_PCK_S_DIV_MSK       (((1U << PSRAM_REG_PCK_S_DIV_LEN) - 1) << PSRAM_REG_PCK_S_DIV_POS)
#define PSRAM_REG_PCK_S_DIV_UMSK      (~(((1U << PSRAM_REG_PCK_S_DIV_LEN) - 1) << PSRAM_REG_PCK_S_DIV_POS))
#define PSRAM_REG_CLKN_FREE           PSRAM_REG_CLKN_FREE
#define PSRAM_REG_CLKN_FREE_POS       (23U)
#define PSRAM_REG_CLKN_FREE_LEN       (1U)
#define PSRAM_REG_CLKN_FREE_MSK       (((1U << PSRAM_REG_CLKN_FREE_LEN) - 1) << PSRAM_REG_CLKN_FREE_POS)
#define PSRAM_REG_CLKN_FREE_UMSK      (~(((1U << PSRAM_REG_CLKN_FREE_LEN) - 1) << PSRAM_REG_CLKN_FREE_POS))
#define PSRAM_REG_LINEAR_BND_B        PSRAM_REG_LINEAR_BND_B
#define PSRAM_REG_LINEAR_BND_B_POS    (28U)
#define PSRAM_REG_LINEAR_BND_B_LEN    (4U)
#define PSRAM_REG_LINEAR_BND_B_MSK    (((1U << PSRAM_REG_LINEAR_BND_B_LEN) - 1) << PSRAM_REG_LINEAR_BND_B_POS)
#define PSRAM_REG_LINEAR_BND_B_UMSK   (~(((1U << PSRAM_REG_LINEAR_BND_B_LEN) - 1) << PSRAM_REG_LINEAR_BND_B_POS))

/* 0x4 : psram_manual_control */
#define PSRAM_MANUAL_CONTROL_OFFSET    (0x4)
#define PSRAM_REG_WC_SW                PSRAM_REG_WC_SW
#define PSRAM_REG_WC_SW_POS            (0U)
#define PSRAM_REG_WC_SW_LEN            (7U)
#define PSRAM_REG_WC_SW_MSK            (((1U << PSRAM_REG_WC_SW_LEN) - 1) << PSRAM_REG_WC_SW_POS)
#define PSRAM_REG_WC_SW_UMSK           (~(((1U << PSRAM_REG_WC_SW_LEN) - 1) << PSRAM_REG_WC_SW_POS))
#define PSRAM_REG_WC_SW_EN             PSRAM_REG_WC_SW_EN
#define PSRAM_REG_WC_SW_EN_POS         (8U)
#define PSRAM_REG_WC_SW_EN_LEN         (1U)
#define PSRAM_REG_WC_SW_EN_MSK         (((1U << PSRAM_REG_WC_SW_EN_LEN) - 1) << PSRAM_REG_WC_SW_EN_POS)
#define PSRAM_REG_WC_SW_EN_UMSK        (~(((1U << PSRAM_REG_WC_SW_EN_LEN) - 1) << PSRAM_REG_WC_SW_EN_POS))
#define PSRAM_REG_STATE_HOLD_TICK      PSRAM_REG_STATE_HOLD_TICK
#define PSRAM_REG_STATE_HOLD_TICK_POS  (9U)
#define PSRAM_REG_STATE_HOLD_TICK_LEN  (1U)
#define PSRAM_REG_STATE_HOLD_TICK_MSK  (((1U << PSRAM_REG_STATE_HOLD_TICK_LEN) - 1) << PSRAM_REG_STATE_HOLD_TICK_POS)
#define PSRAM_REG_STATE_HOLD_TICK_UMSK (~(((1U << PSRAM_REG_STATE_HOLD_TICK_LEN) - 1) << PSRAM_REG_STATE_HOLD_TICK_POS))
#define PSRAM_REG_DQS_LATCH_INV        PSRAM_REG_DQS_LATCH_INV
#define PSRAM_REG_DQS_LATCH_INV_POS    (10U)
#define PSRAM_REG_DQS_LATCH_INV_LEN    (1U)
#define PSRAM_REG_DQS_LATCH_INV_MSK    (((1U << PSRAM_REG_DQS_LATCH_INV_LEN) - 1) << PSRAM_REG_DQS_LATCH_INV_POS)
#define PSRAM_REG_DQS_LATCH_INV_UMSK   (~(((1U << PSRAM_REG_DQS_LATCH_INV_LEN) - 1) << PSRAM_REG_DQS_LATCH_INV_POS))
#define PSRAM_REG_WB_BL2_MASK          PSRAM_REG_WB_BL2_MASK
#define PSRAM_REG_WB_BL2_MASK_POS      (11U)
#define PSRAM_REG_WB_BL2_MASK_LEN      (1U)
#define PSRAM_REG_WB_BL2_MASK_MSK      (((1U << PSRAM_REG_WB_BL2_MASK_LEN) - 1) << PSRAM_REG_WB_BL2_MASK_POS)
#define PSRAM_REG_WB_BL2_MASK_UMSK     (~(((1U << PSRAM_REG_WB_BL2_MASK_LEN) - 1) << PSRAM_REG_WB_BL2_MASK_POS))
#define PSRAM_REG_FORCE_CEB_LOW        PSRAM_REG_FORCE_CEB_LOW
#define PSRAM_REG_FORCE_CEB_LOW_POS    (12U)
#define PSRAM_REG_FORCE_CEB_LOW_LEN    (1U)
#define PSRAM_REG_FORCE_CEB_LOW_MSK    (((1U << PSRAM_REG_FORCE_CEB_LOW_LEN) - 1) << PSRAM_REG_FORCE_CEB_LOW_POS)
#define PSRAM_REG_FORCE_CEB_LOW_UMSK   (~(((1U << PSRAM_REG_FORCE_CEB_LOW_LEN) - 1) << PSRAM_REG_FORCE_CEB_LOW_POS))
#define PSRAM_REG_FORCE_CEB_HIGH       PSRAM_REG_FORCE_CEB_HIGH
#define PSRAM_REG_FORCE_CEB_HIGH_POS   (13U)
#define PSRAM_REG_FORCE_CEB_HIGH_LEN   (1U)
#define PSRAM_REG_FORCE_CEB_HIGH_MSK   (((1U << PSRAM_REG_FORCE_CEB_HIGH_LEN) - 1) << PSRAM_REG_FORCE_CEB_HIGH_POS)
#define PSRAM_REG_FORCE_CEB_HIGH_UMSK  (~(((1U << PSRAM_REG_FORCE_CEB_HIGH_LEN) - 1) << PSRAM_REG_FORCE_CEB_HIGH_POS))
#define PSRAM_REG_PSRAM_RESETB         PSRAM_REG_PSRAM_RESETB
#define PSRAM_REG_PSRAM_RESETB_POS     (14U)
#define PSRAM_REG_PSRAM_RESETB_LEN     (1U)
#define PSRAM_REG_PSRAM_RESETB_MSK     (((1U << PSRAM_REG_PSRAM_RESETB_LEN) - 1) << PSRAM_REG_PSRAM_RESETB_POS)
#define PSRAM_REG_PSRAM_RESETB_UMSK    (~(((1U << PSRAM_REG_PSRAM_RESETB_LEN) - 1) << PSRAM_REG_PSRAM_RESETB_POS))
#define PSRAM_REG_CK_EDGE_NALI         PSRAM_REG_CK_EDGE_NALI
#define PSRAM_REG_CK_EDGE_NALI_POS     (15U)
#define PSRAM_REG_CK_EDGE_NALI_LEN     (1U)
#define PSRAM_REG_CK_EDGE_NALI_MSK     (((1U << PSRAM_REG_CK_EDGE_NALI_LEN) - 1) << PSRAM_REG_CK_EDGE_NALI_POS)
#define PSRAM_REG_CK_EDGE_NALI_UMSK    (~(((1U << PSRAM_REG_CK_EDGE_NALI_LEN) - 1) << PSRAM_REG_CK_EDGE_NALI_POS))
#define PSRAM_STS_CONFIG_READ          PSRAM_STS_CONFIG_READ
#define PSRAM_STS_CONFIG_READ_POS      (16U)
#define PSRAM_STS_CONFIG_READ_LEN      (16U)
#define PSRAM_STS_CONFIG_READ_MSK      (((1U << PSRAM_STS_CONFIG_READ_LEN) - 1) << PSRAM_STS_CONFIG_READ_POS)
#define PSRAM_STS_CONFIG_READ_UMSK     (~(((1U << PSRAM_STS_CONFIG_READ_LEN) - 1) << PSRAM_STS_CONFIG_READ_POS))

/* 0x8 : fifo_thres_control */
#define PSRAM_FIFO_THRES_CONTROL_OFFSET (0x8)
#define PSRAM_REG_MASK_W_FIFO_CNT       PSRAM_REG_MASK_W_FIFO_CNT
#define PSRAM_REG_MASK_W_FIFO_CNT_POS   (0U)
#define PSRAM_REG_MASK_W_FIFO_CNT_LEN   (16U)
#define PSRAM_REG_MASK_W_FIFO_CNT_MSK   (((1U << PSRAM_REG_MASK_W_FIFO_CNT_LEN) - 1) << PSRAM_REG_MASK_W_FIFO_CNT_POS)
#define PSRAM_REG_MASK_W_FIFO_CNT_UMSK  (~(((1U << PSRAM_REG_MASK_W_FIFO_CNT_LEN) - 1) << PSRAM_REG_MASK_W_FIFO_CNT_POS))
#define PSRAM_REG_MASK_R_FIFO_REM       PSRAM_REG_MASK_R_FIFO_REM
#define PSRAM_REG_MASK_R_FIFO_REM_POS   (16U)
#define PSRAM_REG_MASK_R_FIFO_REM_LEN   (16U)
#define PSRAM_REG_MASK_R_FIFO_REM_MSK   (((1U << PSRAM_REG_MASK_R_FIFO_REM_LEN) - 1) << PSRAM_REG_MASK_R_FIFO_REM_POS)
#define PSRAM_REG_MASK_R_FIFO_REM_UMSK  (~(((1U << PSRAM_REG_MASK_R_FIFO_REM_LEN) - 1) << PSRAM_REG_MASK_R_FIFO_REM_POS))

/* 0xC : psram_manual_control2 */
#define PSRAM_MANUAL_CONTROL2_OFFSET  (0xC)
#define PSRAM_REG_HOLD_CYCLE_SW       PSRAM_REG_HOLD_CYCLE_SW
#define PSRAM_REG_HOLD_CYCLE_SW_POS   (0U)
#define PSRAM_REG_HOLD_CYCLE_SW_LEN   (7U)
#define PSRAM_REG_HOLD_CYCLE_SW_MSK   (((1U << PSRAM_REG_HOLD_CYCLE_SW_LEN) - 1) << PSRAM_REG_HOLD_CYCLE_SW_POS)
#define PSRAM_REG_HOLD_CYCLE_SW_UMSK  (~(((1U << PSRAM_REG_HOLD_CYCLE_SW_LEN) - 1) << PSRAM_REG_HOLD_CYCLE_SW_POS))
#define PSRAM_REG_HC_SW_EN            PSRAM_REG_HC_SW_EN
#define PSRAM_REG_HC_SW_EN_POS        (7U)
#define PSRAM_REG_HC_SW_EN_LEN        (1U)
#define PSRAM_REG_HC_SW_EN_MSK        (((1U << PSRAM_REG_HC_SW_EN_LEN) - 1) << PSRAM_REG_HC_SW_EN_POS)
#define PSRAM_REG_HC_SW_EN_UMSK       (~(((1U << PSRAM_REG_HC_SW_EN_LEN) - 1) << PSRAM_REG_HC_SW_EN_POS))
#define PSRAM_REG_DQS_REL_VAL         PSRAM_REG_DQS_REL_VAL
#define PSRAM_REG_DQS_REL_VAL_POS     (8U)
#define PSRAM_REG_DQS_REL_VAL_LEN     (7U)
#define PSRAM_REG_DQS_REL_VAL_MSK     (((1U << PSRAM_REG_DQS_REL_VAL_LEN) - 1) << PSRAM_REG_DQS_REL_VAL_POS)
#define PSRAM_REG_DQS_REL_VAL_UMSK    (~(((1U << PSRAM_REG_DQS_REL_VAL_LEN) - 1) << PSRAM_REG_DQS_REL_VAL_POS))
#define PSRAM_REG_PWRAP_SW_SHT_B      PSRAM_REG_PWRAP_SW_SHT_B
#define PSRAM_REG_PWRAP_SW_SHT_B_POS  (16U)
#define PSRAM_REG_PWRAP_SW_SHT_B_LEN  (4U)
#define PSRAM_REG_PWRAP_SW_SHT_B_MSK  (((1U << PSRAM_REG_PWRAP_SW_SHT_B_LEN) - 1) << PSRAM_REG_PWRAP_SW_SHT_B_POS)
#define PSRAM_REG_PWRAP_SW_SHT_B_UMSK (~(((1U << PSRAM_REG_PWRAP_SW_SHT_B_LEN) - 1) << PSRAM_REG_PWRAP_SW_SHT_B_POS))
#define PSRAM_REG_PWRAP_SW_EN         PSRAM_REG_PWRAP_SW_EN
#define PSRAM_REG_PWRAP_SW_EN_POS     (23U)
#define PSRAM_REG_PWRAP_SW_EN_LEN     (1U)
#define PSRAM_REG_PWRAP_SW_EN_MSK     (((1U << PSRAM_REG_PWRAP_SW_EN_LEN) - 1) << PSRAM_REG_PWRAP_SW_EN_POS)
#define PSRAM_REG_PWRAP_SW_EN_UMSK    (~(((1U << PSRAM_REG_PWRAP_SW_EN_LEN) - 1) << PSRAM_REG_PWRAP_SW_EN_POS))
#define PSRAM_REG_ADDR_MASK           PSRAM_REG_ADDR_MASK
#define PSRAM_REG_ADDR_MASK_POS       (24U)
#define PSRAM_REG_ADDR_MASK_LEN       (8U)
#define PSRAM_REG_ADDR_MASK_MSK       (((1U << PSRAM_REG_ADDR_MASK_LEN) - 1) << PSRAM_REG_ADDR_MASK_POS)
#define PSRAM_REG_ADDR_MASK_UMSK      (~(((1U << PSRAM_REG_ADDR_MASK_LEN) - 1) << PSRAM_REG_ADDR_MASK_POS))

/* 0x10 : winbond_psram_configure */
#define PSRAM_WINBOND_PSRAM_CONFIGURE_OFFSET (0x10)
#define PSRAM_REG_WB_LATENCY                 PSRAM_REG_WB_LATENCY
#define PSRAM_REG_WB_LATENCY_POS             (0U)
#define PSRAM_REG_WB_LATENCY_LEN             (4U)
#define PSRAM_REG_WB_LATENCY_MSK             (((1U << PSRAM_REG_WB_LATENCY_LEN) - 1) << PSRAM_REG_WB_LATENCY_POS)
#define PSRAM_REG_WB_LATENCY_UMSK            (~(((1U << PSRAM_REG_WB_LATENCY_LEN) - 1) << PSRAM_REG_WB_LATENCY_POS))
#define PSRAM_REG_WB_DRIVE_ST                PSRAM_REG_WB_DRIVE_ST
#define PSRAM_REG_WB_DRIVE_ST_POS            (4U)
#define PSRAM_REG_WB_DRIVE_ST_LEN            (3U)
#define PSRAM_REG_WB_DRIVE_ST_MSK            (((1U << PSRAM_REG_WB_DRIVE_ST_LEN) - 1) << PSRAM_REG_WB_DRIVE_ST_POS)
#define PSRAM_REG_WB_DRIVE_ST_UMSK           (~(((1U << PSRAM_REG_WB_DRIVE_ST_LEN) - 1) << PSRAM_REG_WB_DRIVE_ST_POS))
#define PSRAM_REG_WB_HYBRID_EN               PSRAM_REG_WB_HYBRID_EN
#define PSRAM_REG_WB_HYBRID_EN_POS           (7U)
#define PSRAM_REG_WB_HYBRID_EN_LEN           (1U)
#define PSRAM_REG_WB_HYBRID_EN_MSK           (((1U << PSRAM_REG_WB_HYBRID_EN_LEN) - 1) << PSRAM_REG_WB_HYBRID_EN_POS)
#define PSRAM_REG_WB_HYBRID_EN_UMSK          (~(((1U << PSRAM_REG_WB_HYBRID_EN_LEN) - 1) << PSRAM_REG_WB_HYBRID_EN_POS))
#define PSRAM_REG_WB_BURST_LENGTH            PSRAM_REG_WB_BURST_LENGTH
#define PSRAM_REG_WB_BURST_LENGTH_POS        (8U)
#define PSRAM_REG_WB_BURST_LENGTH_LEN        (3U)
#define PSRAM_REG_WB_BURST_LENGTH_MSK        (((1U << PSRAM_REG_WB_BURST_LENGTH_LEN) - 1) << PSRAM_REG_WB_BURST_LENGTH_POS)
#define PSRAM_REG_WB_BURST_LENGTH_UMSK       (~(((1U << PSRAM_REG_WB_BURST_LENGTH_LEN) - 1) << PSRAM_REG_WB_BURST_LENGTH_POS))
#define PSRAM_REG_WB_FIX_LATENCY             PSRAM_REG_WB_FIX_LATENCY
#define PSRAM_REG_WB_FIX_LATENCY_POS         (12U)
#define PSRAM_REG_WB_FIX_LATENCY_LEN         (1U)
#define PSRAM_REG_WB_FIX_LATENCY_MSK         (((1U << PSRAM_REG_WB_FIX_LATENCY_LEN) - 1) << PSRAM_REG_WB_FIX_LATENCY_POS)
#define PSRAM_REG_WB_FIX_LATENCY_UMSK        (~(((1U << PSRAM_REG_WB_FIX_LATENCY_LEN) - 1) << PSRAM_REG_WB_FIX_LATENCY_POS))
#define PSRAM_REG_WB_DPD_DIS                 PSRAM_REG_WB_DPD_DIS
#define PSRAM_REG_WB_DPD_DIS_POS             (13U)
#define PSRAM_REG_WB_DPD_DIS_LEN             (1U)
#define PSRAM_REG_WB_DPD_DIS_MSK             (((1U << PSRAM_REG_WB_DPD_DIS_LEN) - 1) << PSRAM_REG_WB_DPD_DIS_POS)
#define PSRAM_REG_WB_DPD_DIS_UMSK            (~(((1U << PSRAM_REG_WB_DPD_DIS_LEN) - 1) << PSRAM_REG_WB_DPD_DIS_POS))
#define PSRAM_REG_WB_PASR                    PSRAM_REG_WB_PASR
#define PSRAM_REG_WB_PASR_POS                (16U)
#define PSRAM_REG_WB_PASR_LEN                (5U)
#define PSRAM_REG_WB_PASR_MSK                (((1U << PSRAM_REG_WB_PASR_LEN) - 1) << PSRAM_REG_WB_PASR_POS)
#define PSRAM_REG_WB_PASR_UMSK               (~(((1U << PSRAM_REG_WB_PASR_LEN) - 1) << PSRAM_REG_WB_PASR_POS))
#define PSRAM_REG_WB_HYBRID_SLP              PSRAM_REG_WB_HYBRID_SLP
#define PSRAM_REG_WB_HYBRID_SLP_POS          (24U)
#define PSRAM_REG_WB_HYBRID_SLP_LEN          (1U)
#define PSRAM_REG_WB_HYBRID_SLP_MSK          (((1U << PSRAM_REG_WB_HYBRID_SLP_LEN) - 1) << PSRAM_REG_WB_HYBRID_SLP_POS)
#define PSRAM_REG_WB_HYBRID_SLP_UMSK         (~(((1U << PSRAM_REG_WB_HYBRID_SLP_LEN) - 1) << PSRAM_REG_WB_HYBRID_SLP_POS))
#define PSRAM_REG_WB_LINEAR_DIS              PSRAM_REG_WB_LINEAR_DIS
#define PSRAM_REG_WB_LINEAR_DIS_POS          (25U)
#define PSRAM_REG_WB_LINEAR_DIS_LEN          (1U)
#define PSRAM_REG_WB_LINEAR_DIS_MSK          (((1U << PSRAM_REG_WB_LINEAR_DIS_LEN) - 1) << PSRAM_REG_WB_LINEAR_DIS_POS)
#define PSRAM_REG_WB_LINEAR_DIS_UMSK         (~(((1U << PSRAM_REG_WB_LINEAR_DIS_LEN) - 1) << PSRAM_REG_WB_LINEAR_DIS_POS))
#define PSRAM_REG_WB_IPD                     PSRAM_REG_WB_IPD
#define PSRAM_REG_WB_IPD_POS                 (29U)
#define PSRAM_REG_WB_IPD_LEN                 (1U)
#define PSRAM_REG_WB_IPD_MSK                 (((1U << PSRAM_REG_WB_IPD_LEN) - 1) << PSRAM_REG_WB_IPD_POS)
#define PSRAM_REG_WB_IPD_UMSK                (~(((1U << PSRAM_REG_WB_IPD_LEN) - 1) << PSRAM_REG_WB_IPD_POS))
#define PSRAM_REG_WB_MCLK_TYPE               PSRAM_REG_WB_MCLK_TYPE
#define PSRAM_REG_WB_MCLK_TYPE_POS           (30U)
#define PSRAM_REG_WB_MCLK_TYPE_LEN           (1U)
#define PSRAM_REG_WB_MCLK_TYPE_MSK           (((1U << PSRAM_REG_WB_MCLK_TYPE_LEN) - 1) << PSRAM_REG_WB_MCLK_TYPE_POS)
#define PSRAM_REG_WB_MCLK_TYPE_UMSK          (~(((1U << PSRAM_REG_WB_MCLK_TYPE_LEN) - 1) << PSRAM_REG_WB_MCLK_TYPE_POS))
#define PSRAM_REG_WB_SW_RST                  PSRAM_REG_WB_SW_RST
#define PSRAM_REG_WB_SW_RST_POS              (31U)
#define PSRAM_REG_WB_SW_RST_LEN              (1U)
#define PSRAM_REG_WB_SW_RST_MSK              (((1U << PSRAM_REG_WB_SW_RST_LEN) - 1) << PSRAM_REG_WB_SW_RST_POS)
#define PSRAM_REG_WB_SW_RST_UMSK             (~(((1U << PSRAM_REG_WB_SW_RST_LEN) - 1) << PSRAM_REG_WB_SW_RST_POS))

/* 0x14 : winbond_psram_status */
#define PSRAM_WINBOND_PSRAM_STATUS_OFFSET (0x14)
#define PSRAM_STS_WB_LATENCY              PSRAM_STS_WB_LATENCY
#define PSRAM_STS_WB_LATENCY_POS          (0U)
#define PSRAM_STS_WB_LATENCY_LEN          (4U)
#define PSRAM_STS_WB_LATENCY_MSK          (((1U << PSRAM_STS_WB_LATENCY_LEN) - 1) << PSRAM_STS_WB_LATENCY_POS)
#define PSRAM_STS_WB_LATENCY_UMSK         (~(((1U << PSRAM_STS_WB_LATENCY_LEN) - 1) << PSRAM_STS_WB_LATENCY_POS))
#define PSRAM_STS_WB_DRIVE_ST             PSRAM_STS_WB_DRIVE_ST
#define PSRAM_STS_WB_DRIVE_ST_POS         (4U)
#define PSRAM_STS_WB_DRIVE_ST_LEN         (3U)
#define PSRAM_STS_WB_DRIVE_ST_MSK         (((1U << PSRAM_STS_WB_DRIVE_ST_LEN) - 1) << PSRAM_STS_WB_DRIVE_ST_POS)
#define PSRAM_STS_WB_DRIVE_ST_UMSK        (~(((1U << PSRAM_STS_WB_DRIVE_ST_LEN) - 1) << PSRAM_STS_WB_DRIVE_ST_POS))
#define PSRAM_STS_WB_HYBRID_EN            PSRAM_STS_WB_HYBRID_EN
#define PSRAM_STS_WB_HYBRID_EN_POS        (7U)
#define PSRAM_STS_WB_HYBRID_EN_LEN        (1U)
#define PSRAM_STS_WB_HYBRID_EN_MSK        (((1U << PSRAM_STS_WB_HYBRID_EN_LEN) - 1) << PSRAM_STS_WB_HYBRID_EN_POS)
#define PSRAM_STS_WB_HYBRID_EN_UMSK       (~(((1U << PSRAM_STS_WB_HYBRID_EN_LEN) - 1) << PSRAM_STS_WB_HYBRID_EN_POS))
#define PSRAM_STS_WB_BURST_LENGTH         PSRAM_STS_WB_BURST_LENGTH
#define PSRAM_STS_WB_BURST_LENGTH_POS     (8U)
#define PSRAM_STS_WB_BURST_LENGTH_LEN     (3U)
#define PSRAM_STS_WB_BURST_LENGTH_MSK     (((1U << PSRAM_STS_WB_BURST_LENGTH_LEN) - 1) << PSRAM_STS_WB_BURST_LENGTH_POS)
#define PSRAM_STS_WB_BURST_LENGTH_UMSK    (~(((1U << PSRAM_STS_WB_BURST_LENGTH_LEN) - 1) << PSRAM_STS_WB_BURST_LENGTH_POS))
#define PSRAM_STS_WB_FIX_LATENCY          PSRAM_STS_WB_FIX_LATENCY
#define PSRAM_STS_WB_FIX_LATENCY_POS      (12U)
#define PSRAM_STS_WB_FIX_LATENCY_LEN      (1U)
#define PSRAM_STS_WB_FIX_LATENCY_MSK      (((1U << PSRAM_STS_WB_FIX_LATENCY_LEN) - 1) << PSRAM_STS_WB_FIX_LATENCY_POS)
#define PSRAM_STS_WB_FIX_LATENCY_UMSK     (~(((1U << PSRAM_STS_WB_FIX_LATENCY_LEN) - 1) << PSRAM_STS_WB_FIX_LATENCY_POS))
#define PSRAM_STS_WB_DPD_DIS              PSRAM_STS_WB_DPD_DIS
#define PSRAM_STS_WB_DPD_DIS_POS          (13U)
#define PSRAM_STS_WB_DPD_DIS_LEN          (1U)
#define PSRAM_STS_WB_DPD_DIS_MSK          (((1U << PSRAM_STS_WB_DPD_DIS_LEN) - 1) << PSRAM_STS_WB_DPD_DIS_POS)
#define PSRAM_STS_WB_DPD_DIS_UMSK         (~(((1U << PSRAM_STS_WB_DPD_DIS_LEN) - 1) << PSRAM_STS_WB_DPD_DIS_POS))
#define PSRAM_STS_WB_PASR                 PSRAM_STS_WB_PASR
#define PSRAM_STS_WB_PASR_POS             (16U)
#define PSRAM_STS_WB_PASR_LEN             (5U)
#define PSRAM_STS_WB_PASR_MSK             (((1U << PSRAM_STS_WB_PASR_LEN) - 1) << PSRAM_STS_WB_PASR_POS)
#define PSRAM_STS_WB_PASR_UMSK            (~(((1U << PSRAM_STS_WB_PASR_LEN) - 1) << PSRAM_STS_WB_PASR_POS))
#define PSRAM_STS_WB_HYBRID_SLP           PSRAM_STS_WB_HYBRID_SLP
#define PSRAM_STS_WB_HYBRID_SLP_POS       (24U)
#define PSRAM_STS_WB_HYBRID_SLP_LEN       (1U)
#define PSRAM_STS_WB_HYBRID_SLP_MSK       (((1U << PSRAM_STS_WB_HYBRID_SLP_LEN) - 1) << PSRAM_STS_WB_HYBRID_SLP_POS)
#define PSRAM_STS_WB_HYBRID_SLP_UMSK      (~(((1U << PSRAM_STS_WB_HYBRID_SLP_LEN) - 1) << PSRAM_STS_WB_HYBRID_SLP_POS))
#define PSRAM_STS_WB_MCLK_TYPE            PSRAM_STS_WB_MCLK_TYPE
#define PSRAM_STS_WB_MCLK_TYPE_POS        (30U)
#define PSRAM_STS_WB_MCLK_TYPE_LEN        (1U)
#define PSRAM_STS_WB_MCLK_TYPE_MSK        (((1U << PSRAM_STS_WB_MCLK_TYPE_LEN) - 1) << PSRAM_STS_WB_MCLK_TYPE_POS)
#define PSRAM_STS_WB_MCLK_TYPE_UMSK       (~(((1U << PSRAM_STS_WB_MCLK_TYPE_LEN) - 1) << PSRAM_STS_WB_MCLK_TYPE_POS))

/* 0x18 : winbond_psram_configure2 */
#define PSRAM_WINBOND_PSRAM_CONFIGURE2_OFFSET (0x18)
#define PSRAM_REG_WB_ZQ_CODE                  PSRAM_REG_WB_ZQ_CODE
#define PSRAM_REG_WB_ZQ_CODE_POS              (0U)
#define PSRAM_REG_WB_ZQ_CODE_LEN              (4U)
#define PSRAM_REG_WB_ZQ_CODE_MSK              (((1U << PSRAM_REG_WB_ZQ_CODE_LEN) - 1) << PSRAM_REG_WB_ZQ_CODE_POS)
#define PSRAM_REG_WB_ZQ_CODE_UMSK             (~(((1U << PSRAM_REG_WB_ZQ_CODE_LEN) - 1) << PSRAM_REG_WB_ZQ_CODE_POS))

/* 0x20 : apmemory_psram_configure */
#define PSRAM_APMEMORY_PSRAM_CONFIGURE_OFFSET (0x20)
#define PSRAM_REG_AP_BURST_LENGTH             PSRAM_REG_AP_BURST_LENGTH
#define PSRAM_REG_AP_BURST_LENGTH_POS         (0U)
#define PSRAM_REG_AP_BURST_LENGTH_LEN         (2U)
#define PSRAM_REG_AP_BURST_LENGTH_MSK         (((1U << PSRAM_REG_AP_BURST_LENGTH_LEN) - 1) << PSRAM_REG_AP_BURST_LENGTH_POS)
#define PSRAM_REG_AP_BURST_LENGTH_UMSK        (~(((1U << PSRAM_REG_AP_BURST_LENGTH_LEN) - 1) << PSRAM_REG_AP_BURST_LENGTH_POS))
#define PSRAM_REG_AP_BURST_TYPE               PSRAM_REG_AP_BURST_TYPE
#define PSRAM_REG_AP_BURST_TYPE_POS           (4U)
#define PSRAM_REG_AP_BURST_TYPE_LEN           (1U)
#define PSRAM_REG_AP_BURST_TYPE_MSK           (((1U << PSRAM_REG_AP_BURST_TYPE_LEN) - 1) << PSRAM_REG_AP_BURST_TYPE_POS)
#define PSRAM_REG_AP_BURST_TYPE_UMSK          (~(((1U << PSRAM_REG_AP_BURST_TYPE_LEN) - 1) << PSRAM_REG_AP_BURST_TYPE_POS))
#define PSRAM_REG_AP_RBX                      PSRAM_REG_AP_RBX
#define PSRAM_REG_AP_RBX_POS                  (5U)
#define PSRAM_REG_AP_RBX_LEN                  (1U)
#define PSRAM_REG_AP_RBX_MSK                  (((1U << PSRAM_REG_AP_RBX_LEN) - 1) << PSRAM_REG_AP_RBX_POS)
#define PSRAM_REG_AP_RBX_UMSK                 (~(((1U << PSRAM_REG_AP_RBX_LEN) - 1) << PSRAM_REG_AP_RBX_POS))
#define PSRAM_REG_AP_DPD                      PSRAM_REG_AP_DPD
#define PSRAM_REG_AP_DPD_POS                  (6U)
#define PSRAM_REG_AP_DPD_LEN                  (1U)
#define PSRAM_REG_AP_DPD_MSK                  (((1U << PSRAM_REG_AP_DPD_LEN) - 1) << PSRAM_REG_AP_DPD_POS)
#define PSRAM_REG_AP_DPD_UMSK                 (~(((1U << PSRAM_REG_AP_DPD_LEN) - 1) << PSRAM_REG_AP_DPD_POS))
#define PSRAM_REG_AP_SLEEP                    PSRAM_REG_AP_SLEEP
#define PSRAM_REG_AP_SLEEP_POS                (7U)
#define PSRAM_REG_AP_SLEEP_LEN                (1U)
#define PSRAM_REG_AP_SLEEP_MSK                (((1U << PSRAM_REG_AP_SLEEP_LEN) - 1) << PSRAM_REG_AP_SLEEP_POS)
#define PSRAM_REG_AP_SLEEP_UMSK               (~(((1U << PSRAM_REG_AP_SLEEP_LEN) - 1) << PSRAM_REG_AP_SLEEP_POS))
#define PSRAM_REG_AP_PASR                     PSRAM_REG_AP_PASR
#define PSRAM_REG_AP_PASR_POS                 (8U)
#define PSRAM_REG_AP_PASR_LEN                 (3U)
#define PSRAM_REG_AP_PASR_MSK                 (((1U << PSRAM_REG_AP_PASR_LEN) - 1) << PSRAM_REG_AP_PASR_POS)
#define PSRAM_REG_AP_PASR_UMSK                (~(((1U << PSRAM_REG_AP_PASR_LEN) - 1) << PSRAM_REG_AP_PASR_POS))
#define PSRAM_REG_AP_W_LATENCY_CODE           PSRAM_REG_AP_W_LATENCY_CODE
#define PSRAM_REG_AP_W_LATENCY_CODE_POS       (12U)
#define PSRAM_REG_AP_W_LATENCY_CODE_LEN       (3U)
#define PSRAM_REG_AP_W_LATENCY_CODE_MSK       (((1U << PSRAM_REG_AP_W_LATENCY_CODE_LEN) - 1) << PSRAM_REG_AP_W_LATENCY_CODE_POS)
#define PSRAM_REG_AP_W_LATENCY_CODE_UMSK      (~(((1U << PSRAM_REG_AP_W_LATENCY_CODE_LEN) - 1) << PSRAM_REG_AP_W_LATENCY_CODE_POS))
#define PSRAM_REG_AP_DRIVE_ST                 PSRAM_REG_AP_DRIVE_ST
#define PSRAM_REG_AP_DRIVE_ST_POS             (16U)
#define PSRAM_REG_AP_DRIVE_ST_LEN             (2U)
#define PSRAM_REG_AP_DRIVE_ST_MSK             (((1U << PSRAM_REG_AP_DRIVE_ST_LEN) - 1) << PSRAM_REG_AP_DRIVE_ST_POS)
#define PSRAM_REG_AP_DRIVE_ST_UMSK            (~(((1U << PSRAM_REG_AP_DRIVE_ST_LEN) - 1) << PSRAM_REG_AP_DRIVE_ST_POS))
#define PSRAM_REG_AP_RF                       PSRAM_REG_AP_RF
#define PSRAM_REG_AP_RF_POS                   (18U)
#define PSRAM_REG_AP_RF_LEN                   (2U)
#define PSRAM_REG_AP_RF_MSK                   (((1U << PSRAM_REG_AP_RF_LEN) - 1) << PSRAM_REG_AP_RF_POS)
#define PSRAM_REG_AP_RF_UMSK                  (~(((1U << PSRAM_REG_AP_RF_LEN) - 1) << PSRAM_REG_AP_RF_POS))
#define PSRAM_REG_AP_R_LATENCY_CODE           PSRAM_REG_AP_R_LATENCY_CODE
#define PSRAM_REG_AP_R_LATENCY_CODE_POS       (20U)
#define PSRAM_REG_AP_R_LATENCY_CODE_LEN       (3U)
#define PSRAM_REG_AP_R_LATENCY_CODE_MSK       (((1U << PSRAM_REG_AP_R_LATENCY_CODE_LEN) - 1) << PSRAM_REG_AP_R_LATENCY_CODE_POS)
#define PSRAM_REG_AP_R_LATENCY_CODE_UMSK      (~(((1U << PSRAM_REG_AP_R_LATENCY_CODE_LEN) - 1) << PSRAM_REG_AP_R_LATENCY_CODE_POS))
#define PSRAM_REG_AP_R_LATENCY_TYPE           PSRAM_REG_AP_R_LATENCY_TYPE
#define PSRAM_REG_AP_R_LATENCY_TYPE_POS       (24U)
#define PSRAM_REG_AP_R_LATENCY_TYPE_LEN       (1U)
#define PSRAM_REG_AP_R_LATENCY_TYPE_MSK       (((1U << PSRAM_REG_AP_R_LATENCY_TYPE_LEN) - 1) << PSRAM_REG_AP_R_LATENCY_TYPE_POS)
#define PSRAM_REG_AP_R_LATENCY_TYPE_UMSK      (~(((1U << PSRAM_REG_AP_R_LATENCY_TYPE_LEN) - 1) << PSRAM_REG_AP_R_LATENCY_TYPE_POS))
#define PSRAM_REG_AP_LINEAR_DIS               PSRAM_REG_AP_LINEAR_DIS
#define PSRAM_REG_AP_LINEAR_DIS_POS           (25U)
#define PSRAM_REG_AP_LINEAR_DIS_LEN           (1U)
#define PSRAM_REG_AP_LINEAR_DIS_MSK           (((1U << PSRAM_REG_AP_LINEAR_DIS_LEN) - 1) << PSRAM_REG_AP_LINEAR_DIS_POS)
#define PSRAM_REG_AP_LINEAR_DIS_UMSK          (~(((1U << PSRAM_REG_AP_LINEAR_DIS_LEN) - 1) << PSRAM_REG_AP_LINEAR_DIS_POS))
#define PSRAM_REG_GLB_RESET_PULSE             PSRAM_REG_GLB_RESET_PULSE
#define PSRAM_REG_GLB_RESET_PULSE_POS         (28U)
#define PSRAM_REG_GLB_RESET_PULSE_LEN         (1U)
#define PSRAM_REG_GLB_RESET_PULSE_MSK         (((1U << PSRAM_REG_GLB_RESET_PULSE_LEN) - 1) << PSRAM_REG_GLB_RESET_PULSE_POS)
#define PSRAM_REG_GLB_RESET_PULSE_UMSK        (~(((1U << PSRAM_REG_GLB_RESET_PULSE_LEN) - 1) << PSRAM_REG_GLB_RESET_PULSE_POS))

/* 0x24 : apmemory_psram_status */
#define PSRAM_APMEMORY_PSRAM_STATUS_OFFSET (0x24)
#define PSRAM_STS_AP_BURST_LENGTH          PSRAM_STS_AP_BURST_LENGTH
#define PSRAM_STS_AP_BURST_LENGTH_POS      (0U)
#define PSRAM_STS_AP_BURST_LENGTH_LEN      (2U)
#define PSRAM_STS_AP_BURST_LENGTH_MSK      (((1U << PSRAM_STS_AP_BURST_LENGTH_LEN) - 1) << PSRAM_STS_AP_BURST_LENGTH_POS)
#define PSRAM_STS_AP_BURST_LENGTH_UMSK     (~(((1U << PSRAM_STS_AP_BURST_LENGTH_LEN) - 1) << PSRAM_STS_AP_BURST_LENGTH_POS))
#define PSRAM_STS_AP_BURST_TYPE            PSRAM_STS_AP_BURST_TYPE
#define PSRAM_STS_AP_BURST_TYPE_POS        (4U)
#define PSRAM_STS_AP_BURST_TYPE_LEN        (1U)
#define PSRAM_STS_AP_BURST_TYPE_MSK        (((1U << PSRAM_STS_AP_BURST_TYPE_LEN) - 1) << PSRAM_STS_AP_BURST_TYPE_POS)
#define PSRAM_STS_AP_BURST_TYPE_UMSK       (~(((1U << PSRAM_STS_AP_BURST_TYPE_LEN) - 1) << PSRAM_STS_AP_BURST_TYPE_POS))
#define PSRAM_STS_AP_RBX                   PSRAM_STS_AP_RBX
#define PSRAM_STS_AP_RBX_POS               (5U)
#define PSRAM_STS_AP_RBX_LEN               (1U)
#define PSRAM_STS_AP_RBX_MSK               (((1U << PSRAM_STS_AP_RBX_LEN) - 1) << PSRAM_STS_AP_RBX_POS)
#define PSRAM_STS_AP_RBX_UMSK              (~(((1U << PSRAM_STS_AP_RBX_LEN) - 1) << PSRAM_STS_AP_RBX_POS))
#define PSRAM_STS_AP_X16_MODE              PSRAM_STS_AP_X16_MODE
#define PSRAM_STS_AP_X16_MODE_POS          (6U)
#define PSRAM_STS_AP_X16_MODE_LEN          (1U)
#define PSRAM_STS_AP_X16_MODE_MSK          (((1U << PSRAM_STS_AP_X16_MODE_LEN) - 1) << PSRAM_STS_AP_X16_MODE_POS)
#define PSRAM_STS_AP_X16_MODE_UMSK         (~(((1U << PSRAM_STS_AP_X16_MODE_LEN) - 1) << PSRAM_STS_AP_X16_MODE_POS))
#define PSRAM_STS_AP_PASR                  PSRAM_STS_AP_PASR
#define PSRAM_STS_AP_PASR_POS              (8U)
#define PSRAM_STS_AP_PASR_LEN              (3U)
#define PSRAM_STS_AP_PASR_MSK              (((1U << PSRAM_STS_AP_PASR_LEN) - 1) << PSRAM_STS_AP_PASR_POS)
#define PSRAM_STS_AP_PASR_UMSK             (~(((1U << PSRAM_STS_AP_PASR_LEN) - 1) << PSRAM_STS_AP_PASR_POS))
#define PSRAM_STS_AP_W_LATENCY_CODE        PSRAM_STS_AP_W_LATENCY_CODE
#define PSRAM_STS_AP_W_LATENCY_CODE_POS    (12U)
#define PSRAM_STS_AP_W_LATENCY_CODE_LEN    (3U)
#define PSRAM_STS_AP_W_LATENCY_CODE_MSK    (((1U << PSRAM_STS_AP_W_LATENCY_CODE_LEN) - 1) << PSRAM_STS_AP_W_LATENCY_CODE_POS)
#define PSRAM_STS_AP_W_LATENCY_CODE_UMSK   (~(((1U << PSRAM_STS_AP_W_LATENCY_CODE_LEN) - 1) << PSRAM_STS_AP_W_LATENCY_CODE_POS))
#define PSRAM_STS_AP_DRIVE_ST              PSRAM_STS_AP_DRIVE_ST
#define PSRAM_STS_AP_DRIVE_ST_POS          (16U)
#define PSRAM_STS_AP_DRIVE_ST_LEN          (2U)
#define PSRAM_STS_AP_DRIVE_ST_MSK          (((1U << PSRAM_STS_AP_DRIVE_ST_LEN) - 1) << PSRAM_STS_AP_DRIVE_ST_POS)
#define PSRAM_STS_AP_DRIVE_ST_UMSK         (~(((1U << PSRAM_STS_AP_DRIVE_ST_LEN) - 1) << PSRAM_STS_AP_DRIVE_ST_POS))
#define PSRAM_STS_AP_RF                    PSRAM_STS_AP_RF
#define PSRAM_STS_AP_RF_POS                (18U)
#define PSRAM_STS_AP_RF_LEN                (2U)
#define PSRAM_STS_AP_RF_MSK                (((1U << PSRAM_STS_AP_RF_LEN) - 1) << PSRAM_STS_AP_RF_POS)
#define PSRAM_STS_AP_RF_UMSK               (~(((1U << PSRAM_STS_AP_RF_LEN) - 1) << PSRAM_STS_AP_RF_POS))
#define PSRAM_STS_AP_R_LATENCY_CODE        PSRAM_STS_AP_R_LATENCY_CODE
#define PSRAM_STS_AP_R_LATENCY_CODE_POS    (20U)
#define PSRAM_STS_AP_R_LATENCY_CODE_LEN    (3U)
#define PSRAM_STS_AP_R_LATENCY_CODE_MSK    (((1U << PSRAM_STS_AP_R_LATENCY_CODE_LEN) - 1) << PSRAM_STS_AP_R_LATENCY_CODE_POS)
#define PSRAM_STS_AP_R_LATENCY_CODE_UMSK   (~(((1U << PSRAM_STS_AP_R_LATENCY_CODE_LEN) - 1) << PSRAM_STS_AP_R_LATENCY_CODE_POS))
#define PSRAM_STS_AP_R_LATENCY_TYPE        PSRAM_STS_AP_R_LATENCY_TYPE
#define PSRAM_STS_AP_R_LATENCY_TYPE_POS    (24U)
#define PSRAM_STS_AP_R_LATENCY_TYPE_LEN    (1U)
#define PSRAM_STS_AP_R_LATENCY_TYPE_MSK    (((1U << PSRAM_STS_AP_R_LATENCY_TYPE_LEN) - 1) << PSRAM_STS_AP_R_LATENCY_TYPE_POS)
#define PSRAM_STS_AP_R_LATENCY_TYPE_UMSK   (~(((1U << PSRAM_STS_AP_R_LATENCY_TYPE_LEN) - 1) << PSRAM_STS_AP_R_LATENCY_TYPE_POS))

/* 0x30 : psram_manual_control3 */
#define PSRAM_MANUAL_CONTROL3_OFFSET    (0x30)
#define PSRAM_REG_ADQ_REL_VAL           PSRAM_REG_ADQ_REL_VAL
#define PSRAM_REG_ADQ_REL_VAL_POS       (0U)
#define PSRAM_REG_ADQ_REL_VAL_LEN       (7U)
#define PSRAM_REG_ADQ_REL_VAL_MSK       (((1U << PSRAM_REG_ADQ_REL_VAL_LEN) - 1) << PSRAM_REG_ADQ_REL_VAL_POS)
#define PSRAM_REG_ADQ_REL_VAL_UMSK      (~(((1U << PSRAM_REG_ADQ_REL_VAL_LEN) - 1) << PSRAM_REG_ADQ_REL_VAL_POS))
#define PSRAM_REG_WRAP2INCR_EN          PSRAM_REG_WRAP2INCR_EN
#define PSRAM_REG_WRAP2INCR_EN_POS      (8U)
#define PSRAM_REG_WRAP2INCR_EN_LEN      (1U)
#define PSRAM_REG_WRAP2INCR_EN_MSK      (((1U << PSRAM_REG_WRAP2INCR_EN_LEN) - 1) << PSRAM_REG_WRAP2INCR_EN_POS)
#define PSRAM_REG_WRAP2INCR_EN_UMSK     (~(((1U << PSRAM_REG_WRAP2INCR_EN_LEN) - 1) << PSRAM_REG_WRAP2INCR_EN_POS))
#define PSRAM_REG_APH_RWDS_THRE_SW      PSRAM_REG_APH_RWDS_THRE_SW
#define PSRAM_REG_APH_RWDS_THRE_SW_POS  (16U)
#define PSRAM_REG_APH_RWDS_THRE_SW_LEN  (6U)
#define PSRAM_REG_APH_RWDS_THRE_SW_MSK  (((1U << PSRAM_REG_APH_RWDS_THRE_SW_LEN) - 1) << PSRAM_REG_APH_RWDS_THRE_SW_POS)
#define PSRAM_REG_APH_RWDS_THRE_SW_UMSK (~(((1U << PSRAM_REG_APH_RWDS_THRE_SW_LEN) - 1) << PSRAM_REG_APH_RWDS_THRE_SW_POS))

/* 0x80 : psram_intf_delay_ctrl0 */
#define PSRAM_INTF_DELAY_CTRL0_OFFSET       (0x80)
#define PSRAM_REG_DELAY_SEL_O_DQS_OEN0      PSRAM_REG_DELAY_SEL_O_DQS_OEN0
#define PSRAM_REG_DELAY_SEL_O_DQS_OEN0_POS  (0U)
#define PSRAM_REG_DELAY_SEL_O_DQS_OEN0_LEN  (8U)
#define PSRAM_REG_DELAY_SEL_O_DQS_OEN0_MSK  (((1U << PSRAM_REG_DELAY_SEL_O_DQS_OEN0_LEN) - 1) << PSRAM_REG_DELAY_SEL_O_DQS_OEN0_POS)
#define PSRAM_REG_DELAY_SEL_O_DQS_OEN0_UMSK (~(((1U << PSRAM_REG_DELAY_SEL_O_DQS_OEN0_LEN) - 1) << PSRAM_REG_DELAY_SEL_O_DQS_OEN0_POS))
#define PSRAM_REG_DELAY_SEL_O_CEB           PSRAM_REG_DELAY_SEL_O_CEB
#define PSRAM_REG_DELAY_SEL_O_CEB_POS       (8U)
#define PSRAM_REG_DELAY_SEL_O_CEB_LEN       (8U)
#define PSRAM_REG_DELAY_SEL_O_CEB_MSK       (((1U << PSRAM_REG_DELAY_SEL_O_CEB_LEN) - 1) << PSRAM_REG_DELAY_SEL_O_CEB_POS)
#define PSRAM_REG_DELAY_SEL_O_CEB_UMSK      (~(((1U << PSRAM_REG_DELAY_SEL_O_CEB_LEN) - 1) << PSRAM_REG_DELAY_SEL_O_CEB_POS))
#define PSRAM_REG_DELAY_SEL_O_CLK_N         PSRAM_REG_DELAY_SEL_O_CLK_N
#define PSRAM_REG_DELAY_SEL_O_CLK_N_POS     (16U)
#define PSRAM_REG_DELAY_SEL_O_CLK_N_LEN     (8U)
#define PSRAM_REG_DELAY_SEL_O_CLK_N_MSK     (((1U << PSRAM_REG_DELAY_SEL_O_CLK_N_LEN) - 1) << PSRAM_REG_DELAY_SEL_O_CLK_N_POS)
#define PSRAM_REG_DELAY_SEL_O_CLK_N_UMSK    (~(((1U << PSRAM_REG_DELAY_SEL_O_CLK_N_LEN) - 1) << PSRAM_REG_DELAY_SEL_O_CLK_N_POS))
#define PSRAM_REG_DELAY_SEL_O_CLK           PSRAM_REG_DELAY_SEL_O_CLK
#define PSRAM_REG_DELAY_SEL_O_CLK_POS       (24U)
#define PSRAM_REG_DELAY_SEL_O_CLK_LEN       (8U)
#define PSRAM_REG_DELAY_SEL_O_CLK_MSK       (((1U << PSRAM_REG_DELAY_SEL_O_CLK_LEN) - 1) << PSRAM_REG_DELAY_SEL_O_CLK_POS)
#define PSRAM_REG_DELAY_SEL_O_CLK_UMSK      (~(((1U << PSRAM_REG_DELAY_SEL_O_CLK_LEN) - 1) << PSRAM_REG_DELAY_SEL_O_CLK_POS))

/* 0x84 : psram_intf_delay_ctrl1 */
#define PSRAM_INTF_DELAY_CTRL1_OFFSET       (0x84)
#define PSRAM_REG_DELAY_SEL_O_ADQ1          PSRAM_REG_DELAY_SEL_O_ADQ1
#define PSRAM_REG_DELAY_SEL_O_ADQ1_POS      (0U)
#define PSRAM_REG_DELAY_SEL_O_ADQ1_LEN      (8U)
#define PSRAM_REG_DELAY_SEL_O_ADQ1_MSK      (((1U << PSRAM_REG_DELAY_SEL_O_ADQ1_LEN) - 1) << PSRAM_REG_DELAY_SEL_O_ADQ1_POS)
#define PSRAM_REG_DELAY_SEL_O_ADQ1_UMSK     (~(((1U << PSRAM_REG_DELAY_SEL_O_ADQ1_LEN) - 1) << PSRAM_REG_DELAY_SEL_O_ADQ1_POS))
#define PSRAM_REG_DELAY_SEL_O_ADQ0          PSRAM_REG_DELAY_SEL_O_ADQ0
#define PSRAM_REG_DELAY_SEL_O_ADQ0_POS      (8U)
#define PSRAM_REG_DELAY_SEL_O_ADQ0_LEN      (8U)
#define PSRAM_REG_DELAY_SEL_O_ADQ0_MSK      (((1U << PSRAM_REG_DELAY_SEL_O_ADQ0_LEN) - 1) << PSRAM_REG_DELAY_SEL_O_ADQ0_POS)
#define PSRAM_REG_DELAY_SEL_O_ADQ0_UMSK     (~(((1U << PSRAM_REG_DELAY_SEL_O_ADQ0_LEN) - 1) << PSRAM_REG_DELAY_SEL_O_ADQ0_POS))
#define PSRAM_REG_DELAY_SEL_O_ADQ_OEN0      PSRAM_REG_DELAY_SEL_O_ADQ_OEN0
#define PSRAM_REG_DELAY_SEL_O_ADQ_OEN0_POS  (16U)
#define PSRAM_REG_DELAY_SEL_O_ADQ_OEN0_LEN  (8U)
#define PSRAM_REG_DELAY_SEL_O_ADQ_OEN0_MSK  (((1U << PSRAM_REG_DELAY_SEL_O_ADQ_OEN0_LEN) - 1) << PSRAM_REG_DELAY_SEL_O_ADQ_OEN0_POS)
#define PSRAM_REG_DELAY_SEL_O_ADQ_OEN0_UMSK (~(((1U << PSRAM_REG_DELAY_SEL_O_ADQ_OEN0_LEN) - 1) << PSRAM_REG_DELAY_SEL_O_ADQ_OEN0_POS))
#define PSRAM_REG_DELAY_SEL_O_DQS0          PSRAM_REG_DELAY_SEL_O_DQS0
#define PSRAM_REG_DELAY_SEL_O_DQS0_POS      (24U)
#define PSRAM_REG_DELAY_SEL_O_DQS0_LEN      (8U)
#define PSRAM_REG_DELAY_SEL_O_DQS0_MSK      (((1U << PSRAM_REG_DELAY_SEL_O_DQS0_LEN) - 1) << PSRAM_REG_DELAY_SEL_O_DQS0_POS)
#define PSRAM_REG_DELAY_SEL_O_DQS0_UMSK     (~(((1U << PSRAM_REG_DELAY_SEL_O_DQS0_LEN) - 1) << PSRAM_REG_DELAY_SEL_O_DQS0_POS))

/* 0x88 : psram_intf_delay_ctrl2 */
#define PSRAM_INTF_DELAY_CTRL2_OFFSET   (0x88)
#define PSRAM_REG_DELAY_SEL_O_ADQ5      PSRAM_REG_DELAY_SEL_O_ADQ5
#define PSRAM_REG_DELAY_SEL_O_ADQ5_POS  (0U)
#define PSRAM_REG_DELAY_SEL_O_ADQ5_LEN  (8U)
#define PSRAM_REG_DELAY_SEL_O_ADQ5_MSK  (((1U << PSRAM_REG_DELAY_SEL_O_ADQ5_LEN) - 1) << PSRAM_REG_DELAY_SEL_O_ADQ5_POS)
#define PSRAM_REG_DELAY_SEL_O_ADQ5_UMSK (~(((1U << PSRAM_REG_DELAY_SEL_O_ADQ5_LEN) - 1) << PSRAM_REG_DELAY_SEL_O_ADQ5_POS))
#define PSRAM_REG_DELAY_SEL_O_ADQ4      PSRAM_REG_DELAY_SEL_O_ADQ4
#define PSRAM_REG_DELAY_SEL_O_ADQ4_POS  (8U)
#define PSRAM_REG_DELAY_SEL_O_ADQ4_LEN  (8U)
#define PSRAM_REG_DELAY_SEL_O_ADQ4_MSK  (((1U << PSRAM_REG_DELAY_SEL_O_ADQ4_LEN) - 1) << PSRAM_REG_DELAY_SEL_O_ADQ4_POS)
#define PSRAM_REG_DELAY_SEL_O_ADQ4_UMSK (~(((1U << PSRAM_REG_DELAY_SEL_O_ADQ4_LEN) - 1) << PSRAM_REG_DELAY_SEL_O_ADQ4_POS))
#define PSRAM_REG_DELAY_SEL_O_ADQ3      PSRAM_REG_DELAY_SEL_O_ADQ3
#define PSRAM_REG_DELAY_SEL_O_ADQ3_POS  (16U)
#define PSRAM_REG_DELAY_SEL_O_ADQ3_LEN  (8U)
#define PSRAM_REG_DELAY_SEL_O_ADQ3_MSK  (((1U << PSRAM_REG_DELAY_SEL_O_ADQ3_LEN) - 1) << PSRAM_REG_DELAY_SEL_O_ADQ3_POS)
#define PSRAM_REG_DELAY_SEL_O_ADQ3_UMSK (~(((1U << PSRAM_REG_DELAY_SEL_O_ADQ3_LEN) - 1) << PSRAM_REG_DELAY_SEL_O_ADQ3_POS))
#define PSRAM_REG_DELAY_SEL_O_ADQ2      PSRAM_REG_DELAY_SEL_O_ADQ2
#define PSRAM_REG_DELAY_SEL_O_ADQ2_POS  (24U)
#define PSRAM_REG_DELAY_SEL_O_ADQ2_LEN  (8U)
#define PSRAM_REG_DELAY_SEL_O_ADQ2_MSK  (((1U << PSRAM_REG_DELAY_SEL_O_ADQ2_LEN) - 1) << PSRAM_REG_DELAY_SEL_O_ADQ2_POS)
#define PSRAM_REG_DELAY_SEL_O_ADQ2_UMSK (~(((1U << PSRAM_REG_DELAY_SEL_O_ADQ2_LEN) - 1) << PSRAM_REG_DELAY_SEL_O_ADQ2_POS))

/* 0x8C : psram_intf_delay_ctrl3 */
#define PSRAM_INTF_DELAY_CTRL3_OFFSET   (0x8C)
#define PSRAM_REG_DELAY_SEL_I_ADQ1      PSRAM_REG_DELAY_SEL_I_ADQ1
#define PSRAM_REG_DELAY_SEL_I_ADQ1_POS  (0U)
#define PSRAM_REG_DELAY_SEL_I_ADQ1_LEN  (8U)
#define PSRAM_REG_DELAY_SEL_I_ADQ1_MSK  (((1U << PSRAM_REG_DELAY_SEL_I_ADQ1_LEN) - 1) << PSRAM_REG_DELAY_SEL_I_ADQ1_POS)
#define PSRAM_REG_DELAY_SEL_I_ADQ1_UMSK (~(((1U << PSRAM_REG_DELAY_SEL_I_ADQ1_LEN) - 1) << PSRAM_REG_DELAY_SEL_I_ADQ1_POS))
#define PSRAM_REG_DELAY_SEL_I_ADQ0      PSRAM_REG_DELAY_SEL_I_ADQ0
#define PSRAM_REG_DELAY_SEL_I_ADQ0_POS  (8U)
#define PSRAM_REG_DELAY_SEL_I_ADQ0_LEN  (8U)
#define PSRAM_REG_DELAY_SEL_I_ADQ0_MSK  (((1U << PSRAM_REG_DELAY_SEL_I_ADQ0_LEN) - 1) << PSRAM_REG_DELAY_SEL_I_ADQ0_POS)
#define PSRAM_REG_DELAY_SEL_I_ADQ0_UMSK (~(((1U << PSRAM_REG_DELAY_SEL_I_ADQ0_LEN) - 1) << PSRAM_REG_DELAY_SEL_I_ADQ0_POS))
#define PSRAM_REG_DELAY_SEL_O_ADQ7      PSRAM_REG_DELAY_SEL_O_ADQ7
#define PSRAM_REG_DELAY_SEL_O_ADQ7_POS  (16U)
#define PSRAM_REG_DELAY_SEL_O_ADQ7_LEN  (8U)
#define PSRAM_REG_DELAY_SEL_O_ADQ7_MSK  (((1U << PSRAM_REG_DELAY_SEL_O_ADQ7_LEN) - 1) << PSRAM_REG_DELAY_SEL_O_ADQ7_POS)
#define PSRAM_REG_DELAY_SEL_O_ADQ7_UMSK (~(((1U << PSRAM_REG_DELAY_SEL_O_ADQ7_LEN) - 1) << PSRAM_REG_DELAY_SEL_O_ADQ7_POS))
#define PSRAM_REG_DELAY_SEL_O_ADQ6      PSRAM_REG_DELAY_SEL_O_ADQ6
#define PSRAM_REG_DELAY_SEL_O_ADQ6_POS  (24U)
#define PSRAM_REG_DELAY_SEL_O_ADQ6_LEN  (8U)
#define PSRAM_REG_DELAY_SEL_O_ADQ6_MSK  (((1U << PSRAM_REG_DELAY_SEL_O_ADQ6_LEN) - 1) << PSRAM_REG_DELAY_SEL_O_ADQ6_POS)
#define PSRAM_REG_DELAY_SEL_O_ADQ6_UMSK (~(((1U << PSRAM_REG_DELAY_SEL_O_ADQ6_LEN) - 1) << PSRAM_REG_DELAY_SEL_O_ADQ6_POS))

/* 0x90 : psram_intf_delay_ctrl4 */
#define PSRAM_INTF_DELAY_CTRL4_OFFSET   (0x90)
#define PSRAM_REG_DELAY_SEL_I_ADQ5      PSRAM_REG_DELAY_SEL_I_ADQ5
#define PSRAM_REG_DELAY_SEL_I_ADQ5_POS  (0U)
#define PSRAM_REG_DELAY_SEL_I_ADQ5_LEN  (8U)
#define PSRAM_REG_DELAY_SEL_I_ADQ5_MSK  (((1U << PSRAM_REG_DELAY_SEL_I_ADQ5_LEN) - 1) << PSRAM_REG_DELAY_SEL_I_ADQ5_POS)
#define PSRAM_REG_DELAY_SEL_I_ADQ5_UMSK (~(((1U << PSRAM_REG_DELAY_SEL_I_ADQ5_LEN) - 1) << PSRAM_REG_DELAY_SEL_I_ADQ5_POS))
#define PSRAM_REG_DELAY_SEL_I_ADQ4      PSRAM_REG_DELAY_SEL_I_ADQ4
#define PSRAM_REG_DELAY_SEL_I_ADQ4_POS  (8U)
#define PSRAM_REG_DELAY_SEL_I_ADQ4_LEN  (8U)
#define PSRAM_REG_DELAY_SEL_I_ADQ4_MSK  (((1U << PSRAM_REG_DELAY_SEL_I_ADQ4_LEN) - 1) << PSRAM_REG_DELAY_SEL_I_ADQ4_POS)
#define PSRAM_REG_DELAY_SEL_I_ADQ4_UMSK (~(((1U << PSRAM_REG_DELAY_SEL_I_ADQ4_LEN) - 1) << PSRAM_REG_DELAY_SEL_I_ADQ4_POS))
#define PSRAM_REG_DELAY_SEL_I_ADQ3      PSRAM_REG_DELAY_SEL_I_ADQ3
#define PSRAM_REG_DELAY_SEL_I_ADQ3_POS  (16U)
#define PSRAM_REG_DELAY_SEL_I_ADQ3_LEN  (8U)
#define PSRAM_REG_DELAY_SEL_I_ADQ3_MSK  (((1U << PSRAM_REG_DELAY_SEL_I_ADQ3_LEN) - 1) << PSRAM_REG_DELAY_SEL_I_ADQ3_POS)
#define PSRAM_REG_DELAY_SEL_I_ADQ3_UMSK (~(((1U << PSRAM_REG_DELAY_SEL_I_ADQ3_LEN) - 1) << PSRAM_REG_DELAY_SEL_I_ADQ3_POS))
#define PSRAM_REG_DELAY_SEL_I_ADQ2      PSRAM_REG_DELAY_SEL_I_ADQ2
#define PSRAM_REG_DELAY_SEL_I_ADQ2_POS  (24U)
#define PSRAM_REG_DELAY_SEL_I_ADQ2_LEN  (8U)
#define PSRAM_REG_DELAY_SEL_I_ADQ2_MSK  (((1U << PSRAM_REG_DELAY_SEL_I_ADQ2_LEN) - 1) << PSRAM_REG_DELAY_SEL_I_ADQ2_POS)
#define PSRAM_REG_DELAY_SEL_I_ADQ2_UMSK (~(((1U << PSRAM_REG_DELAY_SEL_I_ADQ2_LEN) - 1) << PSRAM_REG_DELAY_SEL_I_ADQ2_POS))

/* 0x94 : psram_intf_delay_ctrl5 */
#define PSRAM_INTF_DELAY_CTRL5_OFFSET   (0x94)
#define PSRAM_REG_DELAY_SEL_I_DQS0      PSRAM_REG_DELAY_SEL_I_DQS0
#define PSRAM_REG_DELAY_SEL_I_DQS0_POS  (0U)
#define PSRAM_REG_DELAY_SEL_I_DQS0_LEN  (16U)
#define PSRAM_REG_DELAY_SEL_I_DQS0_MSK  (((1U << PSRAM_REG_DELAY_SEL_I_DQS0_LEN) - 1) << PSRAM_REG_DELAY_SEL_I_DQS0_POS)
#define PSRAM_REG_DELAY_SEL_I_DQS0_UMSK (~(((1U << PSRAM_REG_DELAY_SEL_I_DQS0_LEN) - 1) << PSRAM_REG_DELAY_SEL_I_DQS0_POS))
#define PSRAM_REG_DELAY_SEL_I_ADQ7      PSRAM_REG_DELAY_SEL_I_ADQ7
#define PSRAM_REG_DELAY_SEL_I_ADQ7_POS  (16U)
#define PSRAM_REG_DELAY_SEL_I_ADQ7_LEN  (8U)
#define PSRAM_REG_DELAY_SEL_I_ADQ7_MSK  (((1U << PSRAM_REG_DELAY_SEL_I_ADQ7_LEN) - 1) << PSRAM_REG_DELAY_SEL_I_ADQ7_POS)
#define PSRAM_REG_DELAY_SEL_I_ADQ7_UMSK (~(((1U << PSRAM_REG_DELAY_SEL_I_ADQ7_LEN) - 1) << PSRAM_REG_DELAY_SEL_I_ADQ7_POS))
#define PSRAM_REG_DELAY_SEL_I_ADQ6      PSRAM_REG_DELAY_SEL_I_ADQ6
#define PSRAM_REG_DELAY_SEL_I_ADQ6_POS  (24U)
#define PSRAM_REG_DELAY_SEL_I_ADQ6_LEN  (8U)
#define PSRAM_REG_DELAY_SEL_I_ADQ6_MSK  (((1U << PSRAM_REG_DELAY_SEL_I_ADQ6_LEN) - 1) << PSRAM_REG_DELAY_SEL_I_ADQ6_POS)
#define PSRAM_REG_DELAY_SEL_I_ADQ6_UMSK (~(((1U << PSRAM_REG_DELAY_SEL_I_ADQ6_LEN) - 1) << PSRAM_REG_DELAY_SEL_I_ADQ6_POS))

/* 0x98 : psram_intf_delay_ctrl6 */
#define PSRAM_INTF_DELAY_CTRL6_OFFSET       (0x98)
#define PSRAM_REG_DELAY_SEL_O_ADQ_OEN1      PSRAM_REG_DELAY_SEL_O_ADQ_OEN1
#define PSRAM_REG_DELAY_SEL_O_ADQ_OEN1_POS  (16U)
#define PSRAM_REG_DELAY_SEL_O_ADQ_OEN1_LEN  (8U)
#define PSRAM_REG_DELAY_SEL_O_ADQ_OEN1_MSK  (((1U << PSRAM_REG_DELAY_SEL_O_ADQ_OEN1_LEN) - 1) << PSRAM_REG_DELAY_SEL_O_ADQ_OEN1_POS)
#define PSRAM_REG_DELAY_SEL_O_ADQ_OEN1_UMSK (~(((1U << PSRAM_REG_DELAY_SEL_O_ADQ_OEN1_LEN) - 1) << PSRAM_REG_DELAY_SEL_O_ADQ_OEN1_POS))
#define PSRAM_REG_DELAY_SEL_O_DQS1          PSRAM_REG_DELAY_SEL_O_DQS1
#define PSRAM_REG_DELAY_SEL_O_DQS1_POS      (24U)
#define PSRAM_REG_DELAY_SEL_O_DQS1_LEN      (8U)
#define PSRAM_REG_DELAY_SEL_O_DQS1_MSK      (((1U << PSRAM_REG_DELAY_SEL_O_DQS1_LEN) - 1) << PSRAM_REG_DELAY_SEL_O_DQS1_POS)
#define PSRAM_REG_DELAY_SEL_O_DQS1_UMSK     (~(((1U << PSRAM_REG_DELAY_SEL_O_DQS1_LEN) - 1) << PSRAM_REG_DELAY_SEL_O_DQS1_POS))

/* 0xAC : psram_intf_delay_ctrlB */
#define PSRAM_INTF_DELAY_CTRLB_OFFSET       (0xAC)
#define PSRAM_REG_DELAY_SEL_O_DQS_MASK      PSRAM_REG_DELAY_SEL_O_DQS_MASK
#define PSRAM_REG_DELAY_SEL_O_DQS_MASK_POS  (0U)
#define PSRAM_REG_DELAY_SEL_O_DQS_MASK_LEN  (8U)
#define PSRAM_REG_DELAY_SEL_O_DQS_MASK_MSK  (((1U << PSRAM_REG_DELAY_SEL_O_DQS_MASK_LEN) - 1) << PSRAM_REG_DELAY_SEL_O_DQS_MASK_POS)
#define PSRAM_REG_DELAY_SEL_O_DQS_MASK_UMSK (~(((1U << PSRAM_REG_DELAY_SEL_O_DQS_MASK_LEN) - 1) << PSRAM_REG_DELAY_SEL_O_DQS_MASK_POS))

/* 0xC0 : psram_dbg_sel */
#define PSRAM_DBG_SEL_OFFSET         (0xC0)
#define PSRAM_REG_PSRAM_DBG_EN       PSRAM_REG_PSRAM_DBG_EN
#define PSRAM_REG_PSRAM_DBG_EN_POS   (0U)
#define PSRAM_REG_PSRAM_DBG_EN_LEN   (1U)
#define PSRAM_REG_PSRAM_DBG_EN_MSK   (((1U << PSRAM_REG_PSRAM_DBG_EN_LEN) - 1) << PSRAM_REG_PSRAM_DBG_EN_POS)
#define PSRAM_REG_PSRAM_DBG_EN_UMSK  (~(((1U << PSRAM_REG_PSRAM_DBG_EN_LEN) - 1) << PSRAM_REG_PSRAM_DBG_EN_POS))
#define PSRAM_REG_PSRAM_DBG_SEL      PSRAM_REG_PSRAM_DBG_SEL
#define PSRAM_REG_PSRAM_DBG_SEL_POS  (4U)
#define PSRAM_REG_PSRAM_DBG_SEL_LEN  (4U)
#define PSRAM_REG_PSRAM_DBG_SEL_MSK  (((1U << PSRAM_REG_PSRAM_DBG_SEL_LEN) - 1) << PSRAM_REG_PSRAM_DBG_SEL_POS)
#define PSRAM_REG_PSRAM_DBG_SEL_UMSK (~(((1U << PSRAM_REG_PSRAM_DBG_SEL_LEN) - 1) << PSRAM_REG_PSRAM_DBG_SEL_POS))

/* 0xF0 : psram_dummy_reg */
#define PSRAM_DUMMY_REG_OFFSET         (0xF0)
#define PSRAM_REG_PSRAM_DUMMY_REG      PSRAM_REG_PSRAM_DUMMY_REG
#define PSRAM_REG_PSRAM_DUMMY_REG_POS  (0U)
#define PSRAM_REG_PSRAM_DUMMY_REG_LEN  (32U)
#define PSRAM_REG_PSRAM_DUMMY_REG_MSK  (((1U << PSRAM_REG_PSRAM_DUMMY_REG_LEN) - 1) << PSRAM_REG_PSRAM_DUMMY_REG_POS)
#define PSRAM_REG_PSRAM_DUMMY_REG_UMSK (~(((1U << PSRAM_REG_PSRAM_DUMMY_REG_LEN) - 1) << PSRAM_REG_PSRAM_DUMMY_REG_POS))

/* 0xF4 : psram_timeout_reg */
#define PSRAM_TIMEOUT_REG_OFFSET   (0xF4)
#define PSRAM_REG_TIMEOUT_EN       PSRAM_REG_TIMEOUT_EN
#define PSRAM_REG_TIMEOUT_EN_POS   (0U)
#define PSRAM_REG_TIMEOUT_EN_LEN   (1U)
#define PSRAM_REG_TIMEOUT_EN_MSK   (((1U << PSRAM_REG_TIMEOUT_EN_LEN) - 1) << PSRAM_REG_TIMEOUT_EN_POS)
#define PSRAM_REG_TIMEOUT_EN_UMSK  (~(((1U << PSRAM_REG_TIMEOUT_EN_LEN) - 1) << PSRAM_REG_TIMEOUT_EN_POS))
#define PSRAM_REG_TIMEOUT_CLR      PSRAM_REG_TIMEOUT_CLR
#define PSRAM_REG_TIMEOUT_CLR_POS  (1U)
#define PSRAM_REG_TIMEOUT_CLR_LEN  (1U)
#define PSRAM_REG_TIMEOUT_CLR_MSK  (((1U << PSRAM_REG_TIMEOUT_CLR_LEN) - 1) << PSRAM_REG_TIMEOUT_CLR_POS)
#define PSRAM_REG_TIMEOUT_CLR_UMSK (~(((1U << PSRAM_REG_TIMEOUT_CLR_LEN) - 1) << PSRAM_REG_TIMEOUT_CLR_POS))
#define PSRAM_STS_TIMEOUT          PSRAM_STS_TIMEOUT
#define PSRAM_STS_TIMEOUT_POS      (2U)
#define PSRAM_STS_TIMEOUT_LEN      (1U)
#define PSRAM_STS_TIMEOUT_MSK      (((1U << PSRAM_STS_TIMEOUT_LEN) - 1) << PSRAM_STS_TIMEOUT_POS)
#define PSRAM_STS_TIMEOUT_UMSK     (~(((1U << PSRAM_STS_TIMEOUT_LEN) - 1) << PSRAM_STS_TIMEOUT_POS))
#define PSRAM_REG_TIMEOUT_CNT      PSRAM_REG_TIMEOUT_CNT
#define PSRAM_REG_TIMEOUT_CNT_POS  (16U)
#define PSRAM_REG_TIMEOUT_CNT_LEN  (12U)
#define PSRAM_REG_TIMEOUT_CNT_MSK  (((1U << PSRAM_REG_TIMEOUT_CNT_LEN) - 1) << PSRAM_REG_TIMEOUT_CNT_POS)
#define PSRAM_REG_TIMEOUT_CNT_UMSK (~(((1U << PSRAM_REG_TIMEOUT_CNT_LEN) - 1) << PSRAM_REG_TIMEOUT_CNT_POS))

/* 0x100 : psram_rough_delay_ctrl0 */
#define PSRAM_ROUGH_DELAY_CTRL0_OFFSET      (0x100)
#define PSRAM_REG_ROUGH_SEL_O_DQS_OEN0      PSRAM_REG_ROUGH_SEL_O_DQS_OEN0
#define PSRAM_REG_ROUGH_SEL_O_DQS_OEN0_POS  (0U)
#define PSRAM_REG_ROUGH_SEL_O_DQS_OEN0_LEN  (8U)
#define PSRAM_REG_ROUGH_SEL_O_DQS_OEN0_MSK  (((1U << PSRAM_REG_ROUGH_SEL_O_DQS_OEN0_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_DQS_OEN0_POS)
#define PSRAM_REG_ROUGH_SEL_O_DQS_OEN0_UMSK (~(((1U << PSRAM_REG_ROUGH_SEL_O_DQS_OEN0_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_DQS_OEN0_POS))
#define PSRAM_REG_ROUGH_SEL_O_CEB           PSRAM_REG_ROUGH_SEL_O_CEB
#define PSRAM_REG_ROUGH_SEL_O_CEB_POS       (8U)
#define PSRAM_REG_ROUGH_SEL_O_CEB_LEN       (8U)
#define PSRAM_REG_ROUGH_SEL_O_CEB_MSK       (((1U << PSRAM_REG_ROUGH_SEL_O_CEB_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_CEB_POS)
#define PSRAM_REG_ROUGH_SEL_O_CEB_UMSK      (~(((1U << PSRAM_REG_ROUGH_SEL_O_CEB_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_CEB_POS))
#define PSRAM_REG_ROUGH_SEL_O_CLK_N         PSRAM_REG_ROUGH_SEL_O_CLK_N
#define PSRAM_REG_ROUGH_SEL_O_CLK_N_POS     (16U)
#define PSRAM_REG_ROUGH_SEL_O_CLK_N_LEN     (8U)
#define PSRAM_REG_ROUGH_SEL_O_CLK_N_MSK     (((1U << PSRAM_REG_ROUGH_SEL_O_CLK_N_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_CLK_N_POS)
#define PSRAM_REG_ROUGH_SEL_O_CLK_N_UMSK    (~(((1U << PSRAM_REG_ROUGH_SEL_O_CLK_N_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_CLK_N_POS))
#define PSRAM_REG_ROUGH_SEL_O_CLK           PSRAM_REG_ROUGH_SEL_O_CLK
#define PSRAM_REG_ROUGH_SEL_O_CLK_POS       (24U)
#define PSRAM_REG_ROUGH_SEL_O_CLK_LEN       (8U)
#define PSRAM_REG_ROUGH_SEL_O_CLK_MSK       (((1U << PSRAM_REG_ROUGH_SEL_O_CLK_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_CLK_POS)
#define PSRAM_REG_ROUGH_SEL_O_CLK_UMSK      (~(((1U << PSRAM_REG_ROUGH_SEL_O_CLK_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_CLK_POS))

/* 0x104 : psram_rough_delay_ctrl1 */
#define PSRAM_ROUGH_DELAY_CTRL1_OFFSET      (0x104)
#define PSRAM_REG_ROUGH_SEL_O_ADQ1          PSRAM_REG_ROUGH_SEL_O_ADQ1
#define PSRAM_REG_ROUGH_SEL_O_ADQ1_POS      (0U)
#define PSRAM_REG_ROUGH_SEL_O_ADQ1_LEN      (8U)
#define PSRAM_REG_ROUGH_SEL_O_ADQ1_MSK      (((1U << PSRAM_REG_ROUGH_SEL_O_ADQ1_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_ADQ1_POS)
#define PSRAM_REG_ROUGH_SEL_O_ADQ1_UMSK     (~(((1U << PSRAM_REG_ROUGH_SEL_O_ADQ1_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_ADQ1_POS))
#define PSRAM_REG_ROUGH_SEL_O_ADQ0          PSRAM_REG_ROUGH_SEL_O_ADQ0
#define PSRAM_REG_ROUGH_SEL_O_ADQ0_POS      (8U)
#define PSRAM_REG_ROUGH_SEL_O_ADQ0_LEN      (8U)
#define PSRAM_REG_ROUGH_SEL_O_ADQ0_MSK      (((1U << PSRAM_REG_ROUGH_SEL_O_ADQ0_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_ADQ0_POS)
#define PSRAM_REG_ROUGH_SEL_O_ADQ0_UMSK     (~(((1U << PSRAM_REG_ROUGH_SEL_O_ADQ0_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_ADQ0_POS))
#define PSRAM_REG_ROUGH_SEL_O_ADQ_OEN0      PSRAM_REG_ROUGH_SEL_O_ADQ_OEN0
#define PSRAM_REG_ROUGH_SEL_O_ADQ_OEN0_POS  (16U)
#define PSRAM_REG_ROUGH_SEL_O_ADQ_OEN0_LEN  (8U)
#define PSRAM_REG_ROUGH_SEL_O_ADQ_OEN0_MSK  (((1U << PSRAM_REG_ROUGH_SEL_O_ADQ_OEN0_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_ADQ_OEN0_POS)
#define PSRAM_REG_ROUGH_SEL_O_ADQ_OEN0_UMSK (~(((1U << PSRAM_REG_ROUGH_SEL_O_ADQ_OEN0_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_ADQ_OEN0_POS))
#define PSRAM_REG_ROUGH_SEL_O_DQS0          PSRAM_REG_ROUGH_SEL_O_DQS0
#define PSRAM_REG_ROUGH_SEL_O_DQS0_POS      (24U)
#define PSRAM_REG_ROUGH_SEL_O_DQS0_LEN      (8U)
#define PSRAM_REG_ROUGH_SEL_O_DQS0_MSK      (((1U << PSRAM_REG_ROUGH_SEL_O_DQS0_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_DQS0_POS)
#define PSRAM_REG_ROUGH_SEL_O_DQS0_UMSK     (~(((1U << PSRAM_REG_ROUGH_SEL_O_DQS0_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_DQS0_POS))

/* 0x108 : psram_rough_delay_ctrl2 */
#define PSRAM_ROUGH_DELAY_CTRL2_OFFSET  (0x108)
#define PSRAM_REG_ROUGH_SEL_O_ADQ5      PSRAM_REG_ROUGH_SEL_O_ADQ5
#define PSRAM_REG_ROUGH_SEL_O_ADQ5_POS  (0U)
#define PSRAM_REG_ROUGH_SEL_O_ADQ5_LEN  (8U)
#define PSRAM_REG_ROUGH_SEL_O_ADQ5_MSK  (((1U << PSRAM_REG_ROUGH_SEL_O_ADQ5_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_ADQ5_POS)
#define PSRAM_REG_ROUGH_SEL_O_ADQ5_UMSK (~(((1U << PSRAM_REG_ROUGH_SEL_O_ADQ5_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_ADQ5_POS))
#define PSRAM_REG_ROUGH_SEL_O_ADQ4      PSRAM_REG_ROUGH_SEL_O_ADQ4
#define PSRAM_REG_ROUGH_SEL_O_ADQ4_POS  (8U)
#define PSRAM_REG_ROUGH_SEL_O_ADQ4_LEN  (8U)
#define PSRAM_REG_ROUGH_SEL_O_ADQ4_MSK  (((1U << PSRAM_REG_ROUGH_SEL_O_ADQ4_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_ADQ4_POS)
#define PSRAM_REG_ROUGH_SEL_O_ADQ4_UMSK (~(((1U << PSRAM_REG_ROUGH_SEL_O_ADQ4_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_ADQ4_POS))
#define PSRAM_REG_ROUGH_SEL_O_ADQ3      PSRAM_REG_ROUGH_SEL_O_ADQ3
#define PSRAM_REG_ROUGH_SEL_O_ADQ3_POS  (16U)
#define PSRAM_REG_ROUGH_SEL_O_ADQ3_LEN  (8U)
#define PSRAM_REG_ROUGH_SEL_O_ADQ3_MSK  (((1U << PSRAM_REG_ROUGH_SEL_O_ADQ3_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_ADQ3_POS)
#define PSRAM_REG_ROUGH_SEL_O_ADQ3_UMSK (~(((1U << PSRAM_REG_ROUGH_SEL_O_ADQ3_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_ADQ3_POS))
#define PSRAM_REG_ROUGH_SEL_O_ADQ2      PSRAM_REG_ROUGH_SEL_O_ADQ2
#define PSRAM_REG_ROUGH_SEL_O_ADQ2_POS  (24U)
#define PSRAM_REG_ROUGH_SEL_O_ADQ2_LEN  (8U)
#define PSRAM_REG_ROUGH_SEL_O_ADQ2_MSK  (((1U << PSRAM_REG_ROUGH_SEL_O_ADQ2_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_ADQ2_POS)
#define PSRAM_REG_ROUGH_SEL_O_ADQ2_UMSK (~(((1U << PSRAM_REG_ROUGH_SEL_O_ADQ2_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_ADQ2_POS))

/* 0x10C : psram_rough_delay_ctrl3 */
#define PSRAM_ROUGH_DELAY_CTRL3_OFFSET  (0x10C)
#define PSRAM_REG_ROUGH_SEL_I_ADQ1      PSRAM_REG_ROUGH_SEL_I_ADQ1
#define PSRAM_REG_ROUGH_SEL_I_ADQ1_POS  (0U)
#define PSRAM_REG_ROUGH_SEL_I_ADQ1_LEN  (8U)
#define PSRAM_REG_ROUGH_SEL_I_ADQ1_MSK  (((1U << PSRAM_REG_ROUGH_SEL_I_ADQ1_LEN) - 1) << PSRAM_REG_ROUGH_SEL_I_ADQ1_POS)
#define PSRAM_REG_ROUGH_SEL_I_ADQ1_UMSK (~(((1U << PSRAM_REG_ROUGH_SEL_I_ADQ1_LEN) - 1) << PSRAM_REG_ROUGH_SEL_I_ADQ1_POS))
#define PSRAM_REG_ROUGH_SEL_I_ADQ0      PSRAM_REG_ROUGH_SEL_I_ADQ0
#define PSRAM_REG_ROUGH_SEL_I_ADQ0_POS  (8U)
#define PSRAM_REG_ROUGH_SEL_I_ADQ0_LEN  (8U)
#define PSRAM_REG_ROUGH_SEL_I_ADQ0_MSK  (((1U << PSRAM_REG_ROUGH_SEL_I_ADQ0_LEN) - 1) << PSRAM_REG_ROUGH_SEL_I_ADQ0_POS)
#define PSRAM_REG_ROUGH_SEL_I_ADQ0_UMSK (~(((1U << PSRAM_REG_ROUGH_SEL_I_ADQ0_LEN) - 1) << PSRAM_REG_ROUGH_SEL_I_ADQ0_POS))
#define PSRAM_REG_ROUGH_SEL_O_ADQ7      PSRAM_REG_ROUGH_SEL_O_ADQ7
#define PSRAM_REG_ROUGH_SEL_O_ADQ7_POS  (16U)
#define PSRAM_REG_ROUGH_SEL_O_ADQ7_LEN  (8U)
#define PSRAM_REG_ROUGH_SEL_O_ADQ7_MSK  (((1U << PSRAM_REG_ROUGH_SEL_O_ADQ7_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_ADQ7_POS)
#define PSRAM_REG_ROUGH_SEL_O_ADQ7_UMSK (~(((1U << PSRAM_REG_ROUGH_SEL_O_ADQ7_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_ADQ7_POS))
#define PSRAM_REG_ROUGH_SEL_O_ADQ6      PSRAM_REG_ROUGH_SEL_O_ADQ6
#define PSRAM_REG_ROUGH_SEL_O_ADQ6_POS  (24U)
#define PSRAM_REG_ROUGH_SEL_O_ADQ6_LEN  (8U)
#define PSRAM_REG_ROUGH_SEL_O_ADQ6_MSK  (((1U << PSRAM_REG_ROUGH_SEL_O_ADQ6_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_ADQ6_POS)
#define PSRAM_REG_ROUGH_SEL_O_ADQ6_UMSK (~(((1U << PSRAM_REG_ROUGH_SEL_O_ADQ6_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_ADQ6_POS))

/* 0x110 : psram_rough_delay_ctrl4 */
#define PSRAM_ROUGH_DELAY_CTRL4_OFFSET  (0x110)
#define PSRAM_REG_ROUGH_SEL_I_ADQ5      PSRAM_REG_ROUGH_SEL_I_ADQ5
#define PSRAM_REG_ROUGH_SEL_I_ADQ5_POS  (0U)
#define PSRAM_REG_ROUGH_SEL_I_ADQ5_LEN  (8U)
#define PSRAM_REG_ROUGH_SEL_I_ADQ5_MSK  (((1U << PSRAM_REG_ROUGH_SEL_I_ADQ5_LEN) - 1) << PSRAM_REG_ROUGH_SEL_I_ADQ5_POS)
#define PSRAM_REG_ROUGH_SEL_I_ADQ5_UMSK (~(((1U << PSRAM_REG_ROUGH_SEL_I_ADQ5_LEN) - 1) << PSRAM_REG_ROUGH_SEL_I_ADQ5_POS))
#define PSRAM_REG_ROUGH_SEL_I_ADQ4      PSRAM_REG_ROUGH_SEL_I_ADQ4
#define PSRAM_REG_ROUGH_SEL_I_ADQ4_POS  (8U)
#define PSRAM_REG_ROUGH_SEL_I_ADQ4_LEN  (8U)
#define PSRAM_REG_ROUGH_SEL_I_ADQ4_MSK  (((1U << PSRAM_REG_ROUGH_SEL_I_ADQ4_LEN) - 1) << PSRAM_REG_ROUGH_SEL_I_ADQ4_POS)
#define PSRAM_REG_ROUGH_SEL_I_ADQ4_UMSK (~(((1U << PSRAM_REG_ROUGH_SEL_I_ADQ4_LEN) - 1) << PSRAM_REG_ROUGH_SEL_I_ADQ4_POS))
#define PSRAM_REG_ROUGH_SEL_I_ADQ3      PSRAM_REG_ROUGH_SEL_I_ADQ3
#define PSRAM_REG_ROUGH_SEL_I_ADQ3_POS  (16U)
#define PSRAM_REG_ROUGH_SEL_I_ADQ3_LEN  (8U)
#define PSRAM_REG_ROUGH_SEL_I_ADQ3_MSK  (((1U << PSRAM_REG_ROUGH_SEL_I_ADQ3_LEN) - 1) << PSRAM_REG_ROUGH_SEL_I_ADQ3_POS)
#define PSRAM_REG_ROUGH_SEL_I_ADQ3_UMSK (~(((1U << PSRAM_REG_ROUGH_SEL_I_ADQ3_LEN) - 1) << PSRAM_REG_ROUGH_SEL_I_ADQ3_POS))
#define PSRAM_REG_ROUGH_SEL_I_ADQ2      PSRAM_REG_ROUGH_SEL_I_ADQ2
#define PSRAM_REG_ROUGH_SEL_I_ADQ2_POS  (24U)
#define PSRAM_REG_ROUGH_SEL_I_ADQ2_LEN  (8U)
#define PSRAM_REG_ROUGH_SEL_I_ADQ2_MSK  (((1U << PSRAM_REG_ROUGH_SEL_I_ADQ2_LEN) - 1) << PSRAM_REG_ROUGH_SEL_I_ADQ2_POS)
#define PSRAM_REG_ROUGH_SEL_I_ADQ2_UMSK (~(((1U << PSRAM_REG_ROUGH_SEL_I_ADQ2_LEN) - 1) << PSRAM_REG_ROUGH_SEL_I_ADQ2_POS))

/* 0x114 : psram_rough_delay_ctrl5 */
#define PSRAM_ROUGH_DELAY_CTRL5_OFFSET  (0x114)
#define PSRAM_REG_ROUGH_SEL_I_DQS0      PSRAM_REG_ROUGH_SEL_I_DQS0
#define PSRAM_REG_ROUGH_SEL_I_DQS0_POS  (0U)
#define PSRAM_REG_ROUGH_SEL_I_DQS0_LEN  (16U)
#define PSRAM_REG_ROUGH_SEL_I_DQS0_MSK  (((1U << PSRAM_REG_ROUGH_SEL_I_DQS0_LEN) - 1) << PSRAM_REG_ROUGH_SEL_I_DQS0_POS)
#define PSRAM_REG_ROUGH_SEL_I_DQS0_UMSK (~(((1U << PSRAM_REG_ROUGH_SEL_I_DQS0_LEN) - 1) << PSRAM_REG_ROUGH_SEL_I_DQS0_POS))
#define PSRAM_REG_ROUGH_SEL_I_ADQ7      PSRAM_REG_ROUGH_SEL_I_ADQ7
#define PSRAM_REG_ROUGH_SEL_I_ADQ7_POS  (16U)
#define PSRAM_REG_ROUGH_SEL_I_ADQ7_LEN  (8U)
#define PSRAM_REG_ROUGH_SEL_I_ADQ7_MSK  (((1U << PSRAM_REG_ROUGH_SEL_I_ADQ7_LEN) - 1) << PSRAM_REG_ROUGH_SEL_I_ADQ7_POS)
#define PSRAM_REG_ROUGH_SEL_I_ADQ7_UMSK (~(((1U << PSRAM_REG_ROUGH_SEL_I_ADQ7_LEN) - 1) << PSRAM_REG_ROUGH_SEL_I_ADQ7_POS))
#define PSRAM_REG_ROUGH_SEL_I_ADQ6      PSRAM_REG_ROUGH_SEL_I_ADQ6
#define PSRAM_REG_ROUGH_SEL_I_ADQ6_POS  (24U)
#define PSRAM_REG_ROUGH_SEL_I_ADQ6_LEN  (8U)
#define PSRAM_REG_ROUGH_SEL_I_ADQ6_MSK  (((1U << PSRAM_REG_ROUGH_SEL_I_ADQ6_LEN) - 1) << PSRAM_REG_ROUGH_SEL_I_ADQ6_POS)
#define PSRAM_REG_ROUGH_SEL_I_ADQ6_UMSK (~(((1U << PSRAM_REG_ROUGH_SEL_I_ADQ6_LEN) - 1) << PSRAM_REG_ROUGH_SEL_I_ADQ6_POS))

/* 0x118 : psram_rough_delay_ctrl6 */
#define PSRAM_ROUGH_DELAY_CTRL6_OFFSET      (0x118)
#define PSRAM_REG_ROUGH_SEL_O_ADQ9          PSRAM_REG_ROUGH_SEL_O_ADQ9
#define PSRAM_REG_ROUGH_SEL_O_ADQ9_POS      (0U)
#define PSRAM_REG_ROUGH_SEL_O_ADQ9_LEN      (8U)
#define PSRAM_REG_ROUGH_SEL_O_ADQ9_MSK      (((1U << PSRAM_REG_ROUGH_SEL_O_ADQ9_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_ADQ9_POS)
#define PSRAM_REG_ROUGH_SEL_O_ADQ9_UMSK     (~(((1U << PSRAM_REG_ROUGH_SEL_O_ADQ9_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_ADQ9_POS))
#define PSRAM_REG_ROUGH_SEL_O_ADQ8          PSRAM_REG_ROUGH_SEL_O_ADQ8
#define PSRAM_REG_ROUGH_SEL_O_ADQ8_POS      (8U)
#define PSRAM_REG_ROUGH_SEL_O_ADQ8_LEN      (8U)
#define PSRAM_REG_ROUGH_SEL_O_ADQ8_MSK      (((1U << PSRAM_REG_ROUGH_SEL_O_ADQ8_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_ADQ8_POS)
#define PSRAM_REG_ROUGH_SEL_O_ADQ8_UMSK     (~(((1U << PSRAM_REG_ROUGH_SEL_O_ADQ8_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_ADQ8_POS))
#define PSRAM_REG_ROUGH_SEL_O_ADQ_OEN1      PSRAM_REG_ROUGH_SEL_O_ADQ_OEN1
#define PSRAM_REG_ROUGH_SEL_O_ADQ_OEN1_POS  (16U)
#define PSRAM_REG_ROUGH_SEL_O_ADQ_OEN1_LEN  (8U)
#define PSRAM_REG_ROUGH_SEL_O_ADQ_OEN1_MSK  (((1U << PSRAM_REG_ROUGH_SEL_O_ADQ_OEN1_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_ADQ_OEN1_POS)
#define PSRAM_REG_ROUGH_SEL_O_ADQ_OEN1_UMSK (~(((1U << PSRAM_REG_ROUGH_SEL_O_ADQ_OEN1_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_ADQ_OEN1_POS))
#define PSRAM_REG_ROUGH_SEL_O_DQS1          PSRAM_REG_ROUGH_SEL_O_DQS1
#define PSRAM_REG_ROUGH_SEL_O_DQS1_POS      (24U)
#define PSRAM_REG_ROUGH_SEL_O_DQS1_LEN      (8U)
#define PSRAM_REG_ROUGH_SEL_O_DQS1_MSK      (((1U << PSRAM_REG_ROUGH_SEL_O_DQS1_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_DQS1_POS)
#define PSRAM_REG_ROUGH_SEL_O_DQS1_UMSK     (~(((1U << PSRAM_REG_ROUGH_SEL_O_DQS1_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_DQS1_POS))

/* 0x11C : psram_rough_delay_ctrl7 */
#define PSRAM_ROUGH_DELAY_CTRL7_OFFSET   (0x11C)
#define PSRAM_REG_ROUGH_SEL_O_ADQ13      PSRAM_REG_ROUGH_SEL_O_ADQ13
#define PSRAM_REG_ROUGH_SEL_O_ADQ13_POS  (0U)
#define PSRAM_REG_ROUGH_SEL_O_ADQ13_LEN  (8U)
#define PSRAM_REG_ROUGH_SEL_O_ADQ13_MSK  (((1U << PSRAM_REG_ROUGH_SEL_O_ADQ13_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_ADQ13_POS)
#define PSRAM_REG_ROUGH_SEL_O_ADQ13_UMSK (~(((1U << PSRAM_REG_ROUGH_SEL_O_ADQ13_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_ADQ13_POS))
#define PSRAM_REG_ROUGH_SEL_O_ADQ12      PSRAM_REG_ROUGH_SEL_O_ADQ12
#define PSRAM_REG_ROUGH_SEL_O_ADQ12_POS  (8U)
#define PSRAM_REG_ROUGH_SEL_O_ADQ12_LEN  (8U)
#define PSRAM_REG_ROUGH_SEL_O_ADQ12_MSK  (((1U << PSRAM_REG_ROUGH_SEL_O_ADQ12_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_ADQ12_POS)
#define PSRAM_REG_ROUGH_SEL_O_ADQ12_UMSK (~(((1U << PSRAM_REG_ROUGH_SEL_O_ADQ12_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_ADQ12_POS))
#define PSRAM_REG_ROUGH_SEL_O_ADQ11      PSRAM_REG_ROUGH_SEL_O_ADQ11
#define PSRAM_REG_ROUGH_SEL_O_ADQ11_POS  (16U)
#define PSRAM_REG_ROUGH_SEL_O_ADQ11_LEN  (8U)
#define PSRAM_REG_ROUGH_SEL_O_ADQ11_MSK  (((1U << PSRAM_REG_ROUGH_SEL_O_ADQ11_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_ADQ11_POS)
#define PSRAM_REG_ROUGH_SEL_O_ADQ11_UMSK (~(((1U << PSRAM_REG_ROUGH_SEL_O_ADQ11_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_ADQ11_POS))
#define PSRAM_REG_ROUGH_SEL_O_ADQ10      PSRAM_REG_ROUGH_SEL_O_ADQ10
#define PSRAM_REG_ROUGH_SEL_O_ADQ10_POS  (24U)
#define PSRAM_REG_ROUGH_SEL_O_ADQ10_LEN  (8U)
#define PSRAM_REG_ROUGH_SEL_O_ADQ10_MSK  (((1U << PSRAM_REG_ROUGH_SEL_O_ADQ10_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_ADQ10_POS)
#define PSRAM_REG_ROUGH_SEL_O_ADQ10_UMSK (~(((1U << PSRAM_REG_ROUGH_SEL_O_ADQ10_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_ADQ10_POS))

/* 0x120 : psram_rough_delay_ctrl8 */
#define PSRAM_ROUGH_DELAY_CTRL8_OFFSET   (0x120)
#define PSRAM_REG_ROUGH_SEL_I_ADQ9       PSRAM_REG_ROUGH_SEL_I_ADQ9
#define PSRAM_REG_ROUGH_SEL_I_ADQ9_POS   (0U)
#define PSRAM_REG_ROUGH_SEL_I_ADQ9_LEN   (8U)
#define PSRAM_REG_ROUGH_SEL_I_ADQ9_MSK   (((1U << PSRAM_REG_ROUGH_SEL_I_ADQ9_LEN) - 1) << PSRAM_REG_ROUGH_SEL_I_ADQ9_POS)
#define PSRAM_REG_ROUGH_SEL_I_ADQ9_UMSK  (~(((1U << PSRAM_REG_ROUGH_SEL_I_ADQ9_LEN) - 1) << PSRAM_REG_ROUGH_SEL_I_ADQ9_POS))
#define PSRAM_REG_ROUGH_SEL_I_ADQ8       PSRAM_REG_ROUGH_SEL_I_ADQ8
#define PSRAM_REG_ROUGH_SEL_I_ADQ8_POS   (8U)
#define PSRAM_REG_ROUGH_SEL_I_ADQ8_LEN   (8U)
#define PSRAM_REG_ROUGH_SEL_I_ADQ8_MSK   (((1U << PSRAM_REG_ROUGH_SEL_I_ADQ8_LEN) - 1) << PSRAM_REG_ROUGH_SEL_I_ADQ8_POS)
#define PSRAM_REG_ROUGH_SEL_I_ADQ8_UMSK  (~(((1U << PSRAM_REG_ROUGH_SEL_I_ADQ8_LEN) - 1) << PSRAM_REG_ROUGH_SEL_I_ADQ8_POS))
#define PSRAM_REG_ROUGH_SEL_O_ADQ15      PSRAM_REG_ROUGH_SEL_O_ADQ15
#define PSRAM_REG_ROUGH_SEL_O_ADQ15_POS  (16U)
#define PSRAM_REG_ROUGH_SEL_O_ADQ15_LEN  (8U)
#define PSRAM_REG_ROUGH_SEL_O_ADQ15_MSK  (((1U << PSRAM_REG_ROUGH_SEL_O_ADQ15_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_ADQ15_POS)
#define PSRAM_REG_ROUGH_SEL_O_ADQ15_UMSK (~(((1U << PSRAM_REG_ROUGH_SEL_O_ADQ15_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_ADQ15_POS))
#define PSRAM_REG_ROUGH_SEL_O_ADQ14      PSRAM_REG_ROUGH_SEL_O_ADQ14
#define PSRAM_REG_ROUGH_SEL_O_ADQ14_POS  (24U)
#define PSRAM_REG_ROUGH_SEL_O_ADQ14_LEN  (8U)
#define PSRAM_REG_ROUGH_SEL_O_ADQ14_MSK  (((1U << PSRAM_REG_ROUGH_SEL_O_ADQ14_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_ADQ14_POS)
#define PSRAM_REG_ROUGH_SEL_O_ADQ14_UMSK (~(((1U << PSRAM_REG_ROUGH_SEL_O_ADQ14_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_ADQ14_POS))

/* 0x124 : psram_rough_delay_ctrl9 */
#define PSRAM_ROUGH_DELAY_CTRL9_OFFSET   (0x124)
#define PSRAM_REG_ROUGH_SEL_I_ADQ13      PSRAM_REG_ROUGH_SEL_I_ADQ13
#define PSRAM_REG_ROUGH_SEL_I_ADQ13_POS  (0U)
#define PSRAM_REG_ROUGH_SEL_I_ADQ13_LEN  (8U)
#define PSRAM_REG_ROUGH_SEL_I_ADQ13_MSK  (((1U << PSRAM_REG_ROUGH_SEL_I_ADQ13_LEN) - 1) << PSRAM_REG_ROUGH_SEL_I_ADQ13_POS)
#define PSRAM_REG_ROUGH_SEL_I_ADQ13_UMSK (~(((1U << PSRAM_REG_ROUGH_SEL_I_ADQ13_LEN) - 1) << PSRAM_REG_ROUGH_SEL_I_ADQ13_POS))
#define PSRAM_REG_ROUGH_SEL_I_ADQ12      PSRAM_REG_ROUGH_SEL_I_ADQ12
#define PSRAM_REG_ROUGH_SEL_I_ADQ12_POS  (8U)
#define PSRAM_REG_ROUGH_SEL_I_ADQ12_LEN  (8U)
#define PSRAM_REG_ROUGH_SEL_I_ADQ12_MSK  (((1U << PSRAM_REG_ROUGH_SEL_I_ADQ12_LEN) - 1) << PSRAM_REG_ROUGH_SEL_I_ADQ12_POS)
#define PSRAM_REG_ROUGH_SEL_I_ADQ12_UMSK (~(((1U << PSRAM_REG_ROUGH_SEL_I_ADQ12_LEN) - 1) << PSRAM_REG_ROUGH_SEL_I_ADQ12_POS))
#define PSRAM_REG_ROUGH_SEL_I_ADQ11      PSRAM_REG_ROUGH_SEL_I_ADQ11
#define PSRAM_REG_ROUGH_SEL_I_ADQ11_POS  (16U)
#define PSRAM_REG_ROUGH_SEL_I_ADQ11_LEN  (8U)
#define PSRAM_REG_ROUGH_SEL_I_ADQ11_MSK  (((1U << PSRAM_REG_ROUGH_SEL_I_ADQ11_LEN) - 1) << PSRAM_REG_ROUGH_SEL_I_ADQ11_POS)
#define PSRAM_REG_ROUGH_SEL_I_ADQ11_UMSK (~(((1U << PSRAM_REG_ROUGH_SEL_I_ADQ11_LEN) - 1) << PSRAM_REG_ROUGH_SEL_I_ADQ11_POS))
#define PSRAM_REG_ROUGH_SEL_I_ADQ10      PSRAM_REG_ROUGH_SEL_I_ADQ10
#define PSRAM_REG_ROUGH_SEL_I_ADQ10_POS  (24U)
#define PSRAM_REG_ROUGH_SEL_I_ADQ10_LEN  (8U)
#define PSRAM_REG_ROUGH_SEL_I_ADQ10_MSK  (((1U << PSRAM_REG_ROUGH_SEL_I_ADQ10_LEN) - 1) << PSRAM_REG_ROUGH_SEL_I_ADQ10_POS)
#define PSRAM_REG_ROUGH_SEL_I_ADQ10_UMSK (~(((1U << PSRAM_REG_ROUGH_SEL_I_ADQ10_LEN) - 1) << PSRAM_REG_ROUGH_SEL_I_ADQ10_POS))

/* 0x128 : psram_rough_delay_ctrlA */
#define PSRAM_ROUGH_DELAY_CTRLA_OFFSET   (0x128)
#define PSRAM_REG_ROUGH_SEL_I_DQS1       PSRAM_REG_ROUGH_SEL_I_DQS1
#define PSRAM_REG_ROUGH_SEL_I_DQS1_POS   (0U)
#define PSRAM_REG_ROUGH_SEL_I_DQS1_LEN   (16U)
#define PSRAM_REG_ROUGH_SEL_I_DQS1_MSK   (((1U << PSRAM_REG_ROUGH_SEL_I_DQS1_LEN) - 1) << PSRAM_REG_ROUGH_SEL_I_DQS1_POS)
#define PSRAM_REG_ROUGH_SEL_I_DQS1_UMSK  (~(((1U << PSRAM_REG_ROUGH_SEL_I_DQS1_LEN) - 1) << PSRAM_REG_ROUGH_SEL_I_DQS1_POS))
#define PSRAM_REG_ROUGH_SEL_I_ADQ15      PSRAM_REG_ROUGH_SEL_I_ADQ15
#define PSRAM_REG_ROUGH_SEL_I_ADQ15_POS  (16U)
#define PSRAM_REG_ROUGH_SEL_I_ADQ15_LEN  (8U)
#define PSRAM_REG_ROUGH_SEL_I_ADQ15_MSK  (((1U << PSRAM_REG_ROUGH_SEL_I_ADQ15_LEN) - 1) << PSRAM_REG_ROUGH_SEL_I_ADQ15_POS)
#define PSRAM_REG_ROUGH_SEL_I_ADQ15_UMSK (~(((1U << PSRAM_REG_ROUGH_SEL_I_ADQ15_LEN) - 1) << PSRAM_REG_ROUGH_SEL_I_ADQ15_POS))
#define PSRAM_REG_ROUGH_SEL_I_ADQ14      PSRAM_REG_ROUGH_SEL_I_ADQ14
#define PSRAM_REG_ROUGH_SEL_I_ADQ14_POS  (24U)
#define PSRAM_REG_ROUGH_SEL_I_ADQ14_LEN  (8U)
#define PSRAM_REG_ROUGH_SEL_I_ADQ14_MSK  (((1U << PSRAM_REG_ROUGH_SEL_I_ADQ14_LEN) - 1) << PSRAM_REG_ROUGH_SEL_I_ADQ14_POS)
#define PSRAM_REG_ROUGH_SEL_I_ADQ14_UMSK (~(((1U << PSRAM_REG_ROUGH_SEL_I_ADQ14_LEN) - 1) << PSRAM_REG_ROUGH_SEL_I_ADQ14_POS))

/* 0x12C : psram_rough_delay_ctrlB */
#define PSRAM_ROUGH_DELAY_CTRLB_OFFSET      (0x12C)
#define PSRAM_REG_ROUGH_SEL_O_DQS_MASK      PSRAM_REG_ROUGH_SEL_O_DQS_MASK
#define PSRAM_REG_ROUGH_SEL_O_DQS_MASK_POS  (0U)
#define PSRAM_REG_ROUGH_SEL_O_DQS_MASK_LEN  (8U)
#define PSRAM_REG_ROUGH_SEL_O_DQS_MASK_MSK  (((1U << PSRAM_REG_ROUGH_SEL_O_DQS_MASK_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_DQS_MASK_POS)
#define PSRAM_REG_ROUGH_SEL_O_DQS_MASK_UMSK (~(((1U << PSRAM_REG_ROUGH_SEL_O_DQS_MASK_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_DQS_MASK_POS))
#define PSRAM_REG_ROUGH_SEL_O_DQS_OEN1      PSRAM_REG_ROUGH_SEL_O_DQS_OEN1
#define PSRAM_REG_ROUGH_SEL_O_DQS_OEN1_POS  (8U)
#define PSRAM_REG_ROUGH_SEL_O_DQS_OEN1_LEN  (8U)
#define PSRAM_REG_ROUGH_SEL_O_DQS_OEN1_MSK  (((1U << PSRAM_REG_ROUGH_SEL_O_DQS_OEN1_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_DQS_OEN1_POS)
#define PSRAM_REG_ROUGH_SEL_O_DQS_OEN1_UMSK (~(((1U << PSRAM_REG_ROUGH_SEL_O_DQS_OEN1_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_DQS_OEN1_POS))

struct psram_reg {
    /* 0x0 : psram_configure */
    union {
        struct {
            uint32_t reg_vendor_sel     : 3; /* [ 2: 0],        r/w,        0x2 */
            uint32_t reserved_3         : 1; /* [    3],       rsvd,        0x0 */
            uint32_t reg_ap_mr          : 3; /* [ 6: 4],        r/w,        0x0 */
            uint32_t reserved_7         : 1; /* [    7],       rsvd,        0x0 */
            uint32_t reg_wb_reg_sel     : 3; /* [10: 8],        r/w,        0x0 */
            uint32_t reserved_11        : 1; /* [   11],       rsvd,        0x0 */
            uint32_t reg_config_w_pusle : 1; /* [   12],        w1p,        0x0 */
            uint32_t reg_config_r_pusle : 1; /* [   13],        w1p,        0x0 */
            uint32_t sts_config_w_done  : 1; /* [   14],          r,        0x1 */
            uint32_t sts_config_r_done  : 1; /* [   15],          r,        0x1 */
            uint32_t reg_config_req     : 1; /* [   16],        r/w,        0x0 */
            uint32_t reg_config_gnt     : 1; /* [   17],          r,        0x0 */
            uint32_t reg_x16_mode       : 1; /* [   18],        r/w,        0x0 */
            uint32_t reg_wb_hyper3      : 1; /* [   19],        r/w,        0x0 */
            uint32_t reg_pck_s_div      : 3; /* [22:20],        r/w,        0x0 */
            uint32_t reg_clkn_free      : 1; /* [   23],        r/w,        0x1 */
            uint32_t reserved_24_27     : 4; /* [27:24],       rsvd,        0x0 */
            uint32_t reg_linear_bnd_b   : 4; /* [31:28],        r/w,        0xa */
        } BF;
        uint32_t WORD;
    } psram_configure;

    /* 0x4 : psram_manual_control */
    union {
        struct {
            uint32_t reg_wc_sw           : 7;  /* [ 6: 0],        r/w,        0x0 */
            uint32_t reserved_7          : 1;  /* [    7],       rsvd,        0x0 */
            uint32_t reg_wc_sw_en        : 1;  /* [    8],        r/w,        0x0 */
            uint32_t reg_state_hold_tick : 1;  /* [    9],        r/w,        0x0 */
            uint32_t reg_dqs_latch_inv   : 1;  /* [   10],        r/w,        0x0 */
            uint32_t reg_wb_bl2_mask     : 1;  /* [   11],        r/w,        0x1 */
            uint32_t reg_force_ceb_low   : 1;  /* [   12],        r/w,        0x0 */
            uint32_t reg_force_ceb_high  : 1;  /* [   13],        r/w,        0x0 */
            uint32_t reg_psram_resetb    : 1;  /* [   14],        r/w,        0x1 */
            uint32_t reg_ck_edge_nali    : 1;  /* [   15],        r/w,        0x0 */
            uint32_t sts_config_read     : 16; /* [31:16],          r,        0x0 */
        } BF;
        uint32_t WORD;
    } psram_manual_control;

    /* 0x8 : fifo_thres_control */
    union {
        struct {
            uint32_t reg_mask_w_fifo_cnt : 16; /* [15: 0],        r/w,        0x0 */
            uint32_t reg_mask_r_fifo_rem : 16; /* [31:16],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } fifo_thres_control;

    /* 0xC : psram_manual_control2 */
    union {
        struct {
            uint32_t reg_hold_cycle_sw  : 7; /* [ 6: 0],        r/w,        0x8 */
            uint32_t reg_hc_sw_en       : 1; /* [    7],        r/w,        0x0 */
            uint32_t reg_dqs_rel_val    : 7; /* [14: 8],        r/w,       0x20 */
            uint32_t reserved_15        : 1; /* [   15],       rsvd,        0x0 */
            uint32_t reg_pwrap_sw_sht_b : 4; /* [19:16],        r/w,        0x8 */
            uint32_t reserved_20_22     : 3; /* [22:20],       rsvd,        0x0 */
            uint32_t reg_pwrap_sw_en    : 1; /* [   23],        r/w,        0x0 */
            uint32_t reg_addr_mask      : 8; /* [31:24],        r/w,       0x1f */
        } BF;
        uint32_t WORD;
    } psram_manual_control2;

    /* 0x10 : winbond_psram_configure */
    union {
        struct {
            uint32_t reg_wb_latency      : 4; /* [ 3: 0],        r/w,        0x2 */
            uint32_t reg_wb_drive_st     : 3; /* [ 6: 4],        r/w,        0x0 */
            uint32_t reg_wb_hybrid_en    : 1; /* [    7],        r/w,        0x1 */
            uint32_t reg_wb_burst_length : 3; /* [10: 8],        r/w,        0x7 */
            uint32_t reserved_11         : 1; /* [   11],       rsvd,        0x0 */
            uint32_t reg_wb_fix_latency  : 1; /* [   12],        r/w,        0x1 */
            uint32_t reg_wb_dpd_dis      : 1; /* [   13],        r/w,        0x1 */
            uint32_t reserved_14_15      : 2; /* [15:14],       rsvd,        0x0 */
            uint32_t reg_wb_pasr         : 5; /* [20:16],        r/w,        0x0 */
            uint32_t reserved_21_23      : 3; /* [23:21],       rsvd,        0x0 */
            uint32_t reg_wb_hybrid_slp   : 1; /* [   24],        r/w,        0x0 */
            uint32_t reg_wb_linear_dis   : 1; /* [   25],        r/w,        0x0 */
            uint32_t reserved_26_28      : 3; /* [28:26],       rsvd,        0x0 */
            uint32_t reg_wb_ipd          : 1; /* [   29],        r/w,        0x0 */
            uint32_t reg_wb_mclk_type    : 1; /* [   30],        r/w,        0x1 */
            uint32_t reg_wb_sw_rst       : 1; /* [   31],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } winbond_psram_configure;

    /* 0x14 : winbond_psram_status */
    union {
        struct {
            uint32_t sts_wb_latency      : 4; /* [ 3: 0],          r,        0x2 */
            uint32_t sts_wb_drive_st     : 3; /* [ 6: 4],          r,        0x0 */
            uint32_t sts_wb_hybrid_en    : 1; /* [    7],          r,        0x1 */
            uint32_t sts_wb_burst_length : 3; /* [10: 8],          r,        0x3 */
            uint32_t reserved_11         : 1; /* [   11],       rsvd,        0x0 */
            uint32_t sts_wb_fix_latency  : 1; /* [   12],          r,        0x1 */
            uint32_t sts_wb_dpd_dis      : 1; /* [   13],          r,        0x1 */
            uint32_t reserved_14_15      : 2; /* [15:14],       rsvd,        0x0 */
            uint32_t sts_wb_pasr         : 5; /* [20:16],          r,        0x0 */
            uint32_t reserved_21_23      : 3; /* [23:21],       rsvd,        0x0 */
            uint32_t sts_wb_hybrid_slp   : 1; /* [   24],          r,        0x0 */
            uint32_t reserved_25_29      : 5; /* [29:25],       rsvd,        0x0 */
            uint32_t sts_wb_mclk_type    : 1; /* [   30],          r,        0x1 */
            uint32_t reserved_31         : 1; /* [   31],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } winbond_psram_status;

    /* 0x18 : winbond_psram_configure2 */
    union {
        struct {
            uint32_t reg_wb_zq_code : 4;  /* [ 3: 0],        r/w,        0x0 */
            uint32_t reserved_4_31  : 28; /* [31: 4],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } winbond_psram_configure2;

    /* 0x1c  reserved */
    uint8_t RESERVED0x1c[4];

    /* 0x20 : apmemory_psram_configure */
    union {
        struct {
            uint32_t reg_ap_burst_length   : 2; /* [ 1: 0],        r/w,        0x1 */
            uint32_t reserved_2_3          : 2; /* [ 3: 2],       rsvd,        0x0 */
            uint32_t reg_ap_burst_type     : 1; /* [    4],        r/w,        0x1 */
            uint32_t reg_ap_rbx            : 1; /* [    5],        r/w,        0x0 */
            uint32_t reg_ap_dpd            : 1; /* [    6],        r/w,        0x0 */
            uint32_t reg_ap_sleep          : 1; /* [    7],        r/w,        0x0 */
            uint32_t reg_ap_pasr           : 3; /* [10: 8],        r/w,        0x0 */
            uint32_t reserved_11           : 1; /* [   11],       rsvd,        0x0 */
            uint32_t reg_ap_w_latency_code : 3; /* [14:12],        r/w,        0x2 */
            uint32_t reserved_15           : 1; /* [   15],       rsvd,        0x0 */
            uint32_t reg_ap_drive_st       : 2; /* [17:16],        r/w,        0x1 */
            uint32_t reg_ap_rf             : 2; /* [19:18],        r/w,        0x0 */
            uint32_t reg_ap_r_latency_code : 3; /* [22:20],        r/w,        0x2 */
            uint32_t reserved_23           : 1; /* [   23],       rsvd,        0x0 */
            uint32_t reg_ap_r_latency_type : 1; /* [   24],        r/w,        0x0 */
            uint32_t reg_ap_linear_dis     : 1; /* [   25],        r/w,        0x0 */
            uint32_t reserved_26_27        : 2; /* [27:26],       rsvd,        0x0 */
            uint32_t reg_glb_reset_pulse   : 1; /* [   28],        w1p,        0x0 */
            uint32_t reserved_29_31        : 3; /* [31:29],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } apmemory_psram_configure;

    /* 0x24 : apmemory_psram_status */
    union {
        struct {
            uint32_t sts_ap_burst_length   : 2; /* [ 1: 0],          r,        0x1 */
            uint32_t reserved_2_3          : 2; /* [ 3: 2],       rsvd,        0x0 */
            uint32_t sts_ap_burst_type     : 1; /* [    4],          r,        0x1 */
            uint32_t sts_ap_rbx            : 1; /* [    5],          r,        0x0 */
            uint32_t sts_ap_x16_mode       : 1; /* [    6],          r,        0x0 */
            uint32_t reserved_7            : 1; /* [    7],       rsvd,        0x0 */
            uint32_t sts_ap_pasr           : 3; /* [10: 8],          r,        0x0 */
            uint32_t reserved_11           : 1; /* [   11],       rsvd,        0x0 */
            uint32_t sts_ap_w_latency_code : 3; /* [14:12],          r,        0x2 */
            uint32_t reserved_15           : 1; /* [   15],       rsvd,        0x0 */
            uint32_t sts_ap_drive_st       : 2; /* [17:16],          r,        0x1 */
            uint32_t sts_ap_rf             : 2; /* [19:18],          r,        0x0 */
            uint32_t sts_ap_r_latency_code : 3; /* [22:20],          r,        0x2 */
            uint32_t reserved_23           : 1; /* [   23],       rsvd,        0x0 */
            uint32_t sts_ap_r_latency_type : 1; /* [   24],          r,        0x0 */
            uint32_t reserved_25_31        : 7; /* [31:25],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } apmemory_psram_status;

    /* 0x28  reserved */
    uint8_t RESERVED0x28[8];

    /* 0x30 : psram_manual_control3 */
    union {
        struct {
            uint32_t reg_adq_rel_val      : 7;  /* [ 6: 0],        r/w,       0x20 */
            uint32_t reserved_7           : 1;  /* [    7],       rsvd,        0x0 */
            uint32_t reg_wrap2incr_en     : 1;  /* [    8],        r/w,        0x1 */
            uint32_t reserved_9_15        : 7;  /* [15: 9],       rsvd,        0x0 */
            uint32_t reg_aph_rwds_thre_sw : 6;  /* [21:16],        r/w,        0x0 */
            uint32_t reserved_22_31       : 10; /* [31:22],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } psram_manual_control3;

    /* 0x34  reserved */
    uint8_t RESERVED0x34[76];

    /* 0x80 : psram_intf_delay_ctrl0 */
    union {
        struct {
            uint32_t reg_delay_sel_o_dqs_oen0 : 8; /* [ 7: 0],        r/w,        0x0 */
            uint32_t reg_delay_sel_o_ceb      : 8; /* [15: 8],        r/w,        0x0 */
            uint32_t reg_delay_sel_o_clk_n    : 8; /* [23:16],        r/w,        0x0 */
            uint32_t reg_delay_sel_o_clk      : 8; /* [31:24],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } psram_intf_delay_ctrl0;

    /* 0x84 : psram_intf_delay_ctrl1 */
    union {
        struct {
            uint32_t reg_delay_sel_o_adq1     : 8; /* [ 7: 0],        r/w,        0x0 */
            uint32_t reg_delay_sel_o_adq0     : 8; /* [15: 8],        r/w,        0x0 */
            uint32_t reg_delay_sel_o_adq_oen0 : 8; /* [23:16],        r/w,        0x0 */
            uint32_t reg_delay_sel_o_dqs0     : 8; /* [31:24],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } psram_intf_delay_ctrl1;

    /* 0x88 : psram_intf_delay_ctrl2 */
    union {
        struct {
            uint32_t reg_delay_sel_o_adq5 : 8; /* [ 7: 0],        r/w,        0x0 */
            uint32_t reg_delay_sel_o_adq4 : 8; /* [15: 8],        r/w,        0x0 */
            uint32_t reg_delay_sel_o_adq3 : 8; /* [23:16],        r/w,        0x0 */
            uint32_t reg_delay_sel_o_adq2 : 8; /* [31:24],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } psram_intf_delay_ctrl2;

    /* 0x8C : psram_intf_delay_ctrl3 */
    union {
        struct {
            uint32_t reg_delay_sel_i_adq1 : 8; /* [ 7: 0],        r/w,        0x0 */
            uint32_t reg_delay_sel_i_adq0 : 8; /* [15: 8],        r/w,        0x0 */
            uint32_t reg_delay_sel_o_adq7 : 8; /* [23:16],        r/w,        0x0 */
            uint32_t reg_delay_sel_o_adq6 : 8; /* [31:24],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } psram_intf_delay_ctrl3;

    /* 0x90 : psram_intf_delay_ctrl4 */
    union {
        struct {
            uint32_t reg_delay_sel_i_adq5 : 8; /* [ 7: 0],        r/w,        0x0 */
            uint32_t reg_delay_sel_i_adq4 : 8; /* [15: 8],        r/w,        0x0 */
            uint32_t reg_delay_sel_i_adq3 : 8; /* [23:16],        r/w,        0x0 */
            uint32_t reg_delay_sel_i_adq2 : 8; /* [31:24],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } psram_intf_delay_ctrl4;

    /* 0x94 : psram_intf_delay_ctrl5 */
    union {
        struct {
            uint32_t reg_delay_sel_i_dqs0 : 16; /* [15: 0],        r/w,        0x0 */
            uint32_t reg_delay_sel_i_adq7 : 8;  /* [23:16],        r/w,        0x0 */
            uint32_t reg_delay_sel_i_adq6 : 8;  /* [31:24],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } psram_intf_delay_ctrl5;

    /* 0x98 : psram_intf_delay_ctrl6 */
    union {
        struct {
            uint32_t reserved_0_15            : 16; /* [15: 0],       rsvd,        0x0 */
            uint32_t reg_delay_sel_o_adq_oen1 : 8;  /* [23:16],        r/w,        0x0 */
            uint32_t reg_delay_sel_o_dqs1     : 8;  /* [31:24],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } psram_intf_delay_ctrl6;

    /* 0x9c  reserved */
    uint8_t RESERVED0x9c[16];

    /* 0xAC : psram_intf_delay_ctrlB */
    union {
        struct {
            uint32_t reg_delay_sel_o_dqs_mask : 8;  /* [ 7: 0],        r/w,        0x0 */
            uint32_t reserved_8_31            : 24; /* [31: 8],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } psram_intf_delay_ctrlB;

    /* 0xb0  reserved */
    uint8_t RESERVED0xb0[16];

    /* 0xC0 : psram_dbg_sel */
    union {
        struct {
            uint32_t reg_psram_dbg_en  : 1;  /* [    0],        r/w,        0x0 */
            uint32_t reserved_1_3      : 3;  /* [ 3: 1],       rsvd,        0x0 */
            uint32_t reg_psram_dbg_sel : 4;  /* [ 7: 4],        r/w,        0x0 */
            uint32_t reserved_8_31     : 24; /* [31: 8],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } psram_dbg_sel;

    /* 0xc4  reserved */
    uint8_t RESERVED0xc4[44];

    /* 0xF0 : psram_dummy_reg */
    union {
        struct {
            uint32_t reg_psram_dummy_reg : 32; /* [31: 0],        r/w, 0xffff0000 */
        } BF;
        uint32_t WORD;
    } psram_dummy_reg;

    /* 0xF4 : psram_timeout_reg */
    union {
        struct {
            uint32_t reg_timeout_en  : 1;  /* [    0],        r/w,        0x0 */
            uint32_t reg_timeout_clr : 1;  /* [    1],        r/w,        0x0 */
            uint32_t sts_timeout     : 1;  /* [    2],          r,        0x0 */
            uint32_t reserved_3_15   : 13; /* [15: 3],       rsvd,        0x0 */
            uint32_t reg_timeout_cnt : 12; /* [27:16],        r/w,      0x100 */
            uint32_t reserved_28_31  : 4;  /* [31:28],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } psram_timeout_reg;

    /* 0xf8  reserved */
    uint8_t RESERVED0xf8[8];

    /* 0x100 : psram_rough_delay_ctrl0 */
    union {
        struct {
            uint32_t reg_rough_sel_o_dqs_oen0 : 8; /* [ 7: 0],        r/w,        0x0 */
            uint32_t reg_rough_sel_o_ceb      : 8; /* [15: 8],        r/w,        0x0 */
            uint32_t reg_rough_sel_o_clk_n    : 8; /* [23:16],        r/w,        0x0 */
            uint32_t reg_rough_sel_o_clk      : 8; /* [31:24],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } psram_rough_delay_ctrl0;

    /* 0x104 : psram_rough_delay_ctrl1 */
    union {
        struct {
            uint32_t reg_rough_sel_o_adq1     : 8; /* [ 7: 0],        r/w,        0x0 */
            uint32_t reg_rough_sel_o_adq0     : 8; /* [15: 8],        r/w,        0x0 */
            uint32_t reg_rough_sel_o_adq_oen0 : 8; /* [23:16],        r/w,        0x0 */
            uint32_t reg_rough_sel_o_dqs0     : 8; /* [31:24],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } psram_rough_delay_ctrl1;

    /* 0x108 : psram_rough_delay_ctrl2 */
    union {
        struct {
            uint32_t reg_rough_sel_o_adq5 : 8; /* [ 7: 0],        r/w,        0x0 */
            uint32_t reg_rough_sel_o_adq4 : 8; /* [15: 8],        r/w,        0x0 */
            uint32_t reg_rough_sel_o_adq3 : 8; /* [23:16],        r/w,        0x0 */
            uint32_t reg_rough_sel_o_adq2 : 8; /* [31:24],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } psram_rough_delay_ctrl2;

    /* 0x10C : psram_rough_delay_ctrl3 */
    union {
        struct {
            uint32_t reg_rough_sel_i_adq1 : 8; /* [ 7: 0],        r/w,        0x0 */
            uint32_t reg_rough_sel_i_adq0 : 8; /* [15: 8],        r/w,        0x0 */
            uint32_t reg_rough_sel_o_adq7 : 8; /* [23:16],        r/w,        0x0 */
            uint32_t reg_rough_sel_o_adq6 : 8; /* [31:24],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } psram_rough_delay_ctrl3;

    /* 0x110 : psram_rough_delay_ctrl4 */
    union {
        struct {
            uint32_t reg_rough_sel_i_adq5 : 8; /* [ 7: 0],        r/w,        0x0 */
            uint32_t reg_rough_sel_i_adq4 : 8; /* [15: 8],        r/w,        0x0 */
            uint32_t reg_rough_sel_i_adq3 : 8; /* [23:16],        r/w,        0x0 */
            uint32_t reg_rough_sel_i_adq2 : 8; /* [31:24],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } psram_rough_delay_ctrl4;

    /* 0x114 : psram_rough_delay_ctrl5 */
    union {
        struct {
            uint32_t reg_rough_sel_i_dqs0 : 16; /* [15: 0],        r/w,        0x0 */
            uint32_t reg_rough_sel_i_adq7 : 8;  /* [23:16],        r/w,        0x0 */
            uint32_t reg_rough_sel_i_adq6 : 8;  /* [31:24],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } psram_rough_delay_ctrl5;

    /* 0x118 : psram_rough_delay_ctrl6 */
    union {
        struct {
            uint32_t reg_rough_sel_o_adq9     : 8; /* [ 7: 0],        r/w,        0x0 */
            uint32_t reg_rough_sel_o_adq8     : 8; /* [15: 8],        r/w,        0x0 */
            uint32_t reg_rough_sel_o_adq_oen1 : 8; /* [23:16],        r/w,        0x0 */
            uint32_t reg_rough_sel_o_dqs1     : 8; /* [31:24],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } psram_rough_delay_ctrl6;

    /* 0x11C : psram_rough_delay_ctrl7 */
    union {
        struct {
            uint32_t reg_rough_sel_o_adq13 : 8; /* [ 7: 0],        r/w,        0x0 */
            uint32_t reg_rough_sel_o_adq12 : 8; /* [15: 8],        r/w,        0x0 */
            uint32_t reg_rough_sel_o_adq11 : 8; /* [23:16],        r/w,        0x0 */
            uint32_t reg_rough_sel_o_adq10 : 8; /* [31:24],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } psram_rough_delay_ctrl7;

    /* 0x120 : psram_rough_delay_ctrl8 */
    union {
        struct {
            uint32_t reg_rough_sel_i_adq9  : 8; /* [ 7: 0],        r/w,        0x0 */
            uint32_t reg_rough_sel_i_adq8  : 8; /* [15: 8],        r/w,        0x0 */
            uint32_t reg_rough_sel_o_adq15 : 8; /* [23:16],        r/w,        0x0 */
            uint32_t reg_rough_sel_o_adq14 : 8; /* [31:24],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } psram_rough_delay_ctrl8;

    /* 0x124 : psram_rough_delay_ctrl9 */
    union {
        struct {
            uint32_t reg_rough_sel_i_adq13 : 8; /* [ 7: 0],        r/w,        0x0 */
            uint32_t reg_rough_sel_i_adq12 : 8; /* [15: 8],        r/w,        0x0 */
            uint32_t reg_rough_sel_i_adq11 : 8; /* [23:16],        r/w,        0x0 */
            uint32_t reg_rough_sel_i_adq10 : 8; /* [31:24],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } psram_rough_delay_ctrl9;

    /* 0x128 : psram_rough_delay_ctrlA */
    union {
        struct {
            uint32_t reg_rough_sel_i_dqs1  : 16; /* [15: 0],        r/w,        0x0 */
            uint32_t reg_rough_sel_i_adq15 : 8;  /* [23:16],        r/w,        0x0 */
            uint32_t reg_rough_sel_i_adq14 : 8;  /* [31:24],        r/w,        0x0 */
        } BF;
        uint32_t WORD;
    } psram_rough_delay_ctrlA;

    /* 0x12C : psram_rough_delay_ctrlB */
    union {
        struct {
            uint32_t reg_rough_sel_o_dqs_mask : 8;  /* [ 7: 0],        r/w,        0x0 */
            uint32_t reg_rough_sel_o_dqs_oen1 : 8;  /* [15: 8],        r/w,        0x0 */
            uint32_t reserved_16_31           : 16; /* [31:16],       rsvd,        0x0 */
        } BF;
        uint32_t WORD;
    } psram_rough_delay_ctrlB;
};

typedef volatile struct psram_reg psram_reg_t;

#endif /* __PSRAM_REG_H__ */
